GPU-Accelerated Simulation of Small Delay Faults
GPU-Accelerated Simulation of Small Delay Faults
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DOI：
10.1109/tcad.2016.2598560
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发表时间：
2017-05
影响因子：
2.9
通讯作者：
E. Schneider;M. Kochte;S. Holst;X. Wen;H. Wunderlich
中科院分区：
文献类型：
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作者：
E. Schneider;M. Kochte;S. Holst;X. Wen;H. Wunderlich
延迟故障仿真是电子电路测试模式生成和可靠性评估过程中的一项重要任务。随着当前纳米级设计对最小延迟偏差的高灵敏度，小栅极延迟故障的模拟变得极其重要。由于这些故障对时序行为有微妙的影响，基于抽象时序模型的传统故障模拟方法是不够的。此外，这些故障的检测受到制造工艺中普遍存在的变化的影响，这导致实际的故障覆盖范围因电路实例而异，并且必须使用定时精确的方法。然而，由于过多的计算要求，定时精确技术的应用很快就变得不可行于较大的设计。在本文中，我们提出了一种对图形处理单元上的小延迟故障进行快速且波形精确的模拟的方法，具有出色的计算性能。通过利用门、故障、波形和电路实例的多个维度的并行性，所提出的方法允许在具有数百万个门的设计的工艺变化下进行定时精确和详尽的小延迟故障模拟。
Delay fault simulation is an essential task during test pattern generation and reliability assessment of electronic circuits. With the high sensitivity of current nano-scale designs toward even smallest delay deviations, the simulation of small gate delay faults has become extremely important. Since these faults have a subtle impact on the timing behavior, traditional fault simulation approaches based on abstract timing models are not sufficient. Furthermore, the detection of these faults is compromised by the ubiquitous variations in the manufacturing processes, which causes the actual fault coverage to vary from circuit instance to circuit instance, and makes the use of timing accurate methods mandatory. However, the application of timing accurate techniques quickly becomes infeasible for larger designs due to excessive computational requirements. In this paper, we present a method for fast and waveform-accurate simulation of small delay faults on graphics processing units with exceptional computational performance. By exploiting multiple dimensions of parallelism from gates, faults, waveforms, and circuit instances, the proposed approach allows for timing-accurate and exhaustive small delay fault simulation under process variation for designs with millions of gates.