Gate-level mitigation techniques for neutron-induced soft error rate
Gate-level mitigation techniques for neutron-induced soft error rate
复制标题
中子引起的软错误率的门级缓解技术
DOI：
10.1109/isqed.2005.61
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
D. Blaauw
中科院分区：
文献类型：
--
作者：
H. Singh;D. Sylvester;D. Blaauw
由于较小的节点电容和降低的操作电压，中子诱导的单粒子翻转在积极缩放的工艺技术中已经变得越来越成问题。我们提出了一个基于概率的分析组合逻辑链上的中子罢工和调查技术，以增加电路的鲁棒性，在降低的概率推翻捕获闩锁给定的粒子罢工。我们表明，使用一种技术，插入简单的交叉耦合逆变器对容易出错的网站，以及智能地放置较低的V/子th/设备和重新调整设备的宽度，可以增加近20%的鲁棒性，从而增加软错误之间的平均时间近25%。与传统的减少软错误的冗余方法相比，这种技术产生的开销要少得多。
Neutron-induced single-event upsets have become increasingly problematic in aggressively scaled process technologies due to smaller nodal capacitances and reduced operating voltages. We present a probability-based analysis of neutron strikes on combinational logic chains and investigate techniques to increase circuit robustness in terms of decreasing the probability of upsetting the capturing latch given a particle strike. We show that using a technique of inserting simple cross-coupled inverter pairs on error prone sites, as well as intelligently placing lower V/sub th/ devices and readjusting device width, can increase the robustness by nearly 20% thereby increasing the mean time between soft errors by almost 25%. This technique incurs substantially less overhead than traditional redundancy approaches to mitigating soft errors.