Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding
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DOI：
10.1109/isqed.2014.6783387
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发表时间：
2014-03
期刊：
影响因子：
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通讯作者：
Ping Chi;Cong Xu;Xiaochun Zhu;Yuan Xie
中科院分区：
文献类型：
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作者：
Ping Chi;Cong Xu;Xiaochun Zhu;Yuan Xie
自旋转移力矩磁阻RAM（STT-MRAM）具有高密度、低泄漏等优点，有望取代传统的SRAM技术，用于构建大尺寸、低功耗的片上高速缓存。具有更高密度的多级单元（MLC）STT-MRAM进一步提高了片上多处理器（CMP）系统的片上高速缓存容量。然而，众所周知的高写入能量阻碍了MLC STT-MRAM的采用。在本文中，我们专注于最大限度地减少MLC STT-MRAM写操作过程中的能量消耗。基于写能量对数据值的强烈依赖性，提出了一种动态编码技术，以在运行时将最频繁出现的数据模式映射到最节能的电阻状态。我们的实验结果表明，与现有的静态数据映射方案相比，我们的技术降低了写能量平均为12.4%，高达25.4%，为一个典型的MLC STT-MRAM缓存。
With attractive advantages like high density and low leakage, Spin-Transfer Torque Magnetoresistive RAM (STT-MRAM) is a promising candidate to replace conventional SRAM technology to build large-size and low-power on-chip caches. Multi-level cell (MLC) STT-MRAM, with a higher density, further improves the on-chip cache capacity for chip multiprocessor (CMP) systems. However, the notorious high write energy impedes the adoption of MLC STT-MRAM. In this paper, we focus on minimizing the energy consumption during MLC STT-MRAM write operations. Based on the strong dependency of write energy on data values, a dynamic encoding technique is proposed to map the most frequently appearing data patterns to the most energy-efficient resistance states at runtime. Our experimental results show that, compared with the existing static data mapping scheme, our technique reduces write energy by 12.4% on average and up to 25.4% for a typical MLC STT-MRAM cache.