Development of a low-noise, two-dimensional amplifier array
Development of a low-noise, two-dimensional amplifier array
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DOI：
10.1016/j.nima.2008.09.043
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发表时间：
2009-01
影响因子：
1.4
通讯作者：
T. Kishishita;H. Ikeda;Takuto Sakumura;K. Tamura;Tadayuki Takahashi
中科院分区：
文献类型：
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作者：
T. Kishishita;H. Ikeda;Takuto Sakumura;K. Tamura;Tadayuki Takahashi
本文介绍了一种低噪声，二维模拟前端ASIC的混合像素成像探测器的最新发展。基于Open-IP LSI项目，该ASIC被设计为满足优于100 e-（rms）的低噪声要求，具有自触发能力。ASIC旨在用于读出像素传感器，该传感器利用硅（Si）和碲化镉（CdTe）作为探测器材料，用于X射线和伽马射线区域的光谱成像观测。读出芯片由4×4矩阵的270μm×270μm像素单元组成，采用TSMC 0.35 μm CMOS工艺实现。每个像素单元包含电荷敏感放大器、零极点消除电路、整形器、比较器和峰值保持电路。ASIC的初步测试实现了88 e-（rms）等效噪声电荷和25 e-/pF噪声斜率，功耗为150μW/像素。
This paper describes the recent development of a low-noise, two-dimensional analog front-end ASIC for hybrid pixel imaging detectors. Based on the Open-IP LSI project, the ASIC is designed to meet a low-noise requirement of better than 100e-(rms) with self-triggering capability. The ASIC is intended for the readout of pixel sensors utilizing silicon (Si) and cadmium telluride (CdTe) as detector materials for spectroscopic imaging observations in the X-ray and gamma-ray regions. The readout chip consists of a 4×4 matrix of identical 270μm×270μm pixel cells and was implemented with TSMC 0.35-μm CMOS technology. Each pixel cell contains a charge-sensitive amplifier, pole-zero cancellation circuit, shaper, comparator, and peak hold circuit. Preliminary testing of the ASIC achieved an 88e-(rms) equivalent noise charge and a 25e-/pF noise slope with power consumption of 150μW per pixel.