Combining variable latency pipeline with instruction reuse for execution latency reduction
Combining variable latency pipeline with instruction reuse for execution latency reduction
复制标题
将可变延迟管道与指令重用相结合以减少执行延迟
DOI：
10.1002/scj.10498
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
I. Arita
中科院分区：
文献类型：
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作者：
Toshinori Sato;I. Arita
操作数旁路逻辑可能是未来微处理器实现高时钟速度的关键结构之一。逻辑延迟导致执行时间预算显著减少，从而将执行阶段划分为几个阶段。可变延迟流水线（VLP）结构具有流水线和伪异步设计的优点。根据传递到算术单元的源操作数，VLP改变执行延迟，从而为大多数操作数实现高速和低延迟。在本文中，我们评估VLP与动态调度超标量处理器，使用一个周期的模拟器。我们的实验结果表明，VLP成功地减少了有效的执行时间，从而放松了对操作数旁路逻辑的约束。我们还评估了指令重用技术，以支持VLP。© 2003威利期刊公司Syst Comp Jpn，34（12）：11-21，2003;在线发表于Wiley InterScience（www.interscience.wiley.com）。DOI 10.1002/scj.10498
Operand bypass logic is likely to be one of the critical structures for future microprocessors to achieve high clock speed. The logic delay causes the execution time budget to be reduced significantly, so that the execution stage is divided into several stages. The variable latency pipeline (VLP) structure has the advantages of pipelining and pseudo-asynchronous design. According to the source operands delivered to arithmetic units, VLP changes execution latency and thus achieves both high speed and low latency for most operands. In this paper we evaluate VLP with dynamically scheduled superscalar processors, using a cycle-by-cycle simulator. Our experimental results show that VLP successfully reduces the effective execution time, and thus relaxes the constraints on the operand bypass logic. We also evaluate the instruction reuse technique in order to support VLP. © 2003 Wiley Periodicals, Inc. Syst Comp Jpn, 34(12): 11–21, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.10498