Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications
Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications
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DOI：
10.1109/leos.2008.4688609
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发表时间：
2008-11
期刊：
影响因子：
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通讯作者：
J. Chan;A. Biberman;Benjamin G. Lee;Keren Bergman
中科院分区：
文献类型：
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作者：
J. Chan;A. Biberman;Benjamin G. Lee;Keren Bergman
片上光子互连网络进行了模拟，以确定不同的网络尺寸和非阻塞开关布局的统计插入损耗。对于一个8times8折叠环面网络，我们得到了15.5 dB的光链路损耗预算。
An on-chip photonic interconnection network is simulated to determine statistical insertion losses for different network sizes and non-blocking switch layouts. For an 8times8 folded-torus network, we obtain an optical link loss budget of 15.5 dB.