Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization
Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization
复制标题
高速 SRAM 字线缓冲器插入优化的自下而上方法
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
Matthew R. Guthaus
中科院分区：
文献类型：
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作者：
Bin Wu;Matthew R. Guthaus
由于连接到位线的每单位长度的高电容，正方形SRAM阵列的延迟由位线延迟主导。因此，SRAM阵列通常在字线方向上较长。然而，在简单的朴素拓扑中，字线延迟也显著增加，并且当字线尺寸比位线的尺寸长得多时，字线延迟可能成为主导因素。因此，字线优化是SRAM延迟优化的重要组成部分。通常用于长互连的缓冲器插入也可用于改善字线延迟。本文提出了一种布局和调整缓冲器大小的方法，以减少字线和总体SRAM延迟。该方法以128kbit的SRAM仅增加5.26%的面积为代价，将读关键路径延迟提高了15.7%。
The delay of a square SRAM array is dominated by the bit line delay due to the high capacitance per unit length attached to the bit line. Hence, SRAM arrays are usually longer in the word line direction. However, the word line delay also increases dramatically in a simple naive topology and can be a dominating factor when the word line dimension is much longer than that of the bit line. Therefore, word line optimization is an important part of SRAM delay optimization. Buffer insertion, which is commonly used for long interconnects, can also be used to improve word line delay. This paper proposes an approach to place and size the buffers to reduce word line and overall SRAM delay. The proposed methodology improves the read critical path delay by 15.7%, at the cost of only 5.26% extra area in a 128 Kbit SRAM.