Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs
Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs
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32nm 高 k/金属栅极 CMOSFET 中频率相关的 TDDB 行为及其可靠性鉴定
DOI：
10.1109/irps.2011.5784445
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
Jongwoo Park
中科院分区：
文献类型：
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作者：
Kyongtaek Lee;J. Nam;M. Jin;Kidan Bae;Junekyun Park;Lira Hwang;Jungin Kim;H. Kim;Jongwoo Park
研究了高k介质/金属栅（HK/MG）CMOSFETs在直流和交流应力条件下的TDDB失效机理，并与poly-Si/锡永进行了比较。单极交流应力下的所有器件都表现出更长的故障时间（tbd），随着频率的增加。在HK/MG的情况下，SILC行为归因于HK中预先存在的缺陷引起的体瞬态电荷捕获。由于一旦施加驰豫偏置，HK中的陷阱电荷就可以很容易地被解除陷阱，因此tbd随着频率变高而增加。与单极AC偏置条件不同，在较低频率下，具有双极AC应力的HK/MG nMOSFET的tbd比具有DC应力的HK/MG nMOSFET短。这归因于空穴捕获到IL中，因为Vg处于栅极注入偏压，因为HK/MG叠层由于相对较低的势垒高度而具有比多晶Si/锡永更高的电子注入概率。然而，高频下的双极AC TDDB显示出比DC TDDB更长的tbd，因为缺乏时间在IL中产生足够的空穴。在双极交流偏置条件下，nMOSFET由于栅注入偏置下空穴产生的Gm退化加剧，而pMOSFET由于衬底注入偏置下体电荷俘获产生的SILC，导致了较高的幂律时间指数（n）。
The TDDB failure mechanism of high-k dielectric/metal gate (HK/MG) CMOSFETs on DC and AC stress conditions are investigated in comparison to poly-Si/SiON. All devices under unipolar AC stress exhibit longer failure time (tbd) as frequency increases. In case of HK/MG, the SILC behavior has been attributed to the bulk transient charge trapping by pre-existing defects in HK. Since trapped charges in HK can easily be detrapped once a relaxation bias is applied, tbd is increased as frequency becomes higher. Unlike unipolar AC bias condition, HK/MG nMOSFETs with bipolar AC stress exhibit shorter tbd than with DC at a lower frequency. This is attributed to hole trapping into IL as Vg is at the gate injection bias since HK/MG stack has higher probability of electron injection than poly-Si/SiON due to relatively lower barrier height. However, bipolar AC TDDB in high frequency shows longer tbd than DC TDDB because of lack of time to generate enough holes in the IL. In bipolar AC bias condition, the higher power-law time exponent (n) appears because Gm degradation by hole generation is aggravated at the gate injection bias in nMOSFET, while pMOSFET SILC is generated by bulk charge trapping at the substrate injection bias.