Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs

Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs
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DOI:
10.1109/isie45552.2021.9576373
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发表时间:
2021-06
期刊:
2021 IEEE 30th International Symposium on Industrial Electronics (ISIE)
影响因子:
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通讯作者:
Koki Abe;Masataka Ishihara;Yusuke Hatakenaka;K. Umetani;E. Hiraki
Koki Abe;Masataka Ishihara;Yusuke Hatakenaka;K. Umetani;E. Hiraki
中科院分区:
其他
文献类型:
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作者:
Koki Abe;Masataka Ishihara;Yusuke Hatakenaka;K. Umetani;E. Hiraki

文献摘要

相似文献

氮化镓场效应管(GaN-FET)具有导通电阻低、开关速度快等优点,有望成为提高电动汽车用开关功率转换器功率密度的关键器件。众所周知,开关损耗受功率环路的寄生电感--漏感的影响,原则上可以通过适当的漏感设计来减小开关损耗。然而,在使用硅基功率器件的开关功率转换器中,例如Si-MOSFET和Si-IGBT,通常很难设计漏感以使开关损耗最小化,因为适当的漏感变得太大,从而导致开关器件的浪涌电压很大。另一方面,当使用GaN-FET时可能不是这种情况,因为由于高di/dt开关,可以最小化开关损耗的电感可能变得很小。因此,本研究的目的是证明寄生漏感设计的可行性,即在保持GaN-FET的浪涌电压在可接受的范围内的同时,最小化桥接电路中GaN-FET的开关损耗。通过仿真验证了该观点的正确性。
Gallium-nitride-field-effect transistors (GaN-FETs) are expected as a key component to the power density improvement of switching power converter for electric vehicles (EVs) because of their low on-resistance and fast switching capability. It is well known that the switching loss is influenced by the drain inductance, which is the parasitic inductance of the power loop, and can be minimized in principle by an appropriate design of the drain inductance. However, in switching power converters using Si-based power devices such as the Si-MOSFET and the Si-IGBT, it is usually difficult to design the drain inductance so that the switching loss minimizes because an appropriate drain inductance becomes too large, thus resulting in large surge voltages of the switching device. On the other hand, this may not be the case when using the GaN-FETs because the inductance that can minimize the switching loss may become small due to the high-di/dt switching. Therefore, the purpose of this study is to show the feasibility of the parasitic drain inductance design that the switching loss of the GaN-FET in the bridge circuit can be minimized while keeping the surge voltage of the GaN-FET within acceptable limits. The appropriateness of this insight is verified by simulation.