Simulation of the electrostatic and transport properties of 3D-stacked GAA silicon nanowire FETs
Simulation of the electrostatic and transport properties of 3D-stacked GAA silicon nanowire FETs
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DOI：
10.1016/j.sse.2011.01.005
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发表时间：
2011-05-01
影响因子：
1.7
通讯作者：
Donetti, L.
中科院分区：
文献类型：
--
作者：
Ruiz, F. G.;Tienda-Luna, I. M.;Donetti, L.
本文基于二维泊松方程和薛定谔方程的自洽解，用模拟方法研究了三维叠层栅通向硅纳米线的静电和输运特性。对这种器件的制造工艺引起的应变效应进行了全面的分析，并与参考触发器器件进行了比较。结果表明，对于小于22 nm的工艺节点，叠层纳米线可以作为触发MOSFET的一种很好的替代方案，这是因为Gate-All-All结构增加了对沟道的栅极静电控制，并且同一晶片表面可以获得更高的总电荷。计算结果还表明，无应变层状NWS的电子迁移率低于触发器的电子迁移率，但在层状NW的制备过程中SiGe层在沟道中产生的应变可以扭转这种情况。(C)2011爱思唯尔有限公司。保留所有权利。
In this work, both the electrostatic and transport features of 3D-stacked Gate-all-Around silicon nanowires are studied using simulations based on a self-consistent solution of the two-dimensional Poisson and Schrodinger equations. A comprehensive analysis of the effect of the strain induced by the fabrication process of such devices is carried out and a comparison made with a reference trigate device. It is shown that stacked nanowires can be a good alternative to trigate MOSFETs for sub-22 nm technology nodes, due to the increased gate electrostatic control of the channel of the Gate-all-Around architecture and to the higher total charge that can be achieved for the same wafer surface. It is also shown that the electron mobility calculated for unstrained stacked NWs is lower than that of trigate devices, but the strain induced in the channels by the SiGe layers during the fabrication process of stacked NWs can overturn this situation. (C) 2011 Elsevier Ltd. All rights reserved.