An on-line reconfigurable FPGA architecture
An on-line reconfigurable FPGA architecture
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一种在线可重构FPGA架构
DOI：
10.1109/dftvs.2000.887167
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发表时间：
2000
期刊：
影响因子：
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通讯作者：
A. Walker
中科院分区：
文献类型：
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作者：
P. Lala;A. Walker
FPGA广泛用于数字系统的原型设计。当前FPGA架构的一个主要问题是，如果在单个组合逻辑块（CLB）中存在故障，则可能需要大量时间来找到电路的替代映射以绕过故障块。因此，需要允许从FPGA中的内部故障快速恢复的新型FPGA架构。目前，在基于FPGA的系统中，仅考虑逻辑块中的永久性故障的检测以及它们的互连。近年来的一些研究表明，在亚微米VLSI器件中，瞬时故障的发生率可能比永久故障高得多。科普FPGA中瞬时故障的唯一方法是在故障发生时立即检测出故障，并执行在线重构以从故障影响中恢复。本文提出了一种可重构的FPGA架构，使在线故障检测的组成CLB的FPGA。
FPGAs are widely used for prototyping of digital systems. A major problem of current FPGA architectures is that if there is a fault in a single combinational logic block (CLB), it may take a significant amount of time to find an alternative mapping of the circuit to bypass the faulty block. Thus, there is a need for new type of FPGA architecture that allows rapid recovery from internal faults in a FPGA. Currently only the detection of permanent faults in logic blocks, and on their interconnections are considered in FPGA-based systems. Several studies in recent years have shown that transient faults are likely to occur at a much higher rate than permanent faults in submicron VLSI devices. The only way to cope with transient faults in FPGAs is to detect them as soon as they occur, and perform on-line reconfiguration to recover from their effects. This paper presents a reconfigurable FPGA architecture that enables on-line fault detection in the constituent CLBs of the FPGA.