Hardware-Software Co-Design for Brain-Computer Interfaces
Hardware-Software Co-Design for Brain-Computer Interfaces
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DOI：
10.1109/isca45697.2020.00041
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发表时间：
2020-05
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通讯作者：
I. Karageorgos;Karthik Sriram;J. Veselý;Michael Wu;M. Powell;D. Borton;R. Manohar;A. Bhattacharjee
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作者：
I. Karageorgos;Karthik Sriram;J. Veselý;Michael Wu;M. Powell;D. Borton;R. Manohar;A. Bhattacharjee
脑机接口（BCI）提供了治疗神经系统疾病的途径，揭示了大脑功能，并将大脑与数字世界连接起来。然而，它们的广泛采用取决于实现足够的实时性能，满足严格的功率限制，并遵守FDA规定的长期植入安全要求。迄今为止，BCI被设计为针对特定疾病或特定大脑区域的特定任务的定制ASIC。通用架构，可用于治疗多种疾病，并使各种计算任务需要更广泛的BCI采用，但传统的智慧是，这样的系统不能满足必要的性能和功耗constrains. HALO（硬件架构低功耗脑机接口），一个通用架构植入式脑机接口。HALO能够实现诸如治疗疾病（例如，癫痫，运动障碍），并记录/处理数据，以促进我们对大脑的理解。我们使用来自非人类灵长类动物运动皮层的电生理数据来确定如何将HALO的计算能力分解为硬件构建模块。我们简化、修剪和共享这些构建块，以明智地使用可用的硬件资源，同时实现多种脑机交互模式。结果是硬件处理元件（PE）的可配置异构阵列。PE由低功耗RISC-V微控制器配置到信号处理管道中，满足广泛安全部署HALO所需的目标性能和功耗限制。
Brain-computer interfaces (BCIs) offer avenues to treat neurological disorders, shed light on brain function, and interface the brain with the digital world. Their wider adoption rests, however, on achieving adequate real-time performance, meeting stringent power constraints, and adhering to FDA-mandated safety requirements for chronic implantation. BCIs have, to date, been designed as custom ASICs for specific diseases or for specific tasks in specific brain regions. General-purpose architectures that can be used to treat multiple diseases and enable various computational tasks are needed for wider BCI adoption, but the conventional wisdom is that such systems cannot meet necessary performance and power constraints.We present HALO (Hardware Architecture for LOw-power BCIs), a general-purpose architecture for implantable BCIs. HALO enables tasks such as treatment of disorders (e.g., epilepsy, movement disorders), and records/processes data for studies that advance our understanding of the brain. We use electrophysiological data from the motor cortex of a non-human primate to determine how to decompose HALO’s computational capabilities into hardware building blocks. We simplify, prune, and share these building blocks to judiciously use available hardware resources while enabling many modes of brain-computer interaction. The result is a configurable heterogeneous array of hardware processing elements (PEs). The PEs are configured by a low-power RISC-V micro-controller into signal processing pipelines that meet the target performance and power constraints necessary to deploy HALO widely and safely.