A low-noise CMOS receiver frontend for MRI
A low-noise CMOS receiver frontend for MRI
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用于 MRI 的低噪声 CMOS 接收器前端
DOI：
10.1109/biocas.2008.4696900
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
G. Boero
中科院分区：
文献类型：
--
作者：
J. Anders;G. Boero
本文描述了一种用于微磁共振成像（micro- mri）应用的集成接收器前端的新架构。当芯片从3.3 V电源中仅消耗9 mA电源电流（LNA为4 mA，输出缓冲器为5 mA）时，其测量输入参考噪声密度仅为0.6 nV/radic（Hz）。接收器由接收线圈、片上调谐电容器、低噪声放大器和50 ω输出缓冲器组成。该系统设计用于在7t的b0场中运行，对应于300 MHz的频率。它在0.35 μ m CMOS高压工艺中实现，占据850 μ m × 500 μ m的芯片面积。
In this paper a novel architecture for an integrated receiver front-end for micro magnetic resonance imaging (micro-MRI) applications is described. While the chip consumes only 9 mA supply current (4 mA in the LNA and 5 mA in the output buffer) from a 3.3 V power supply, it has a measured input referred noise density of only 0.6 nV/radic(Hz). The receiver consists of a reception coil, an on-chip tuning capacitor, a low-noise amplifier, and a 50 Omega output buffer. The system is designed for operation in a B0-field of 7 T corresponding to a frequency of 300 MHz. It is implemented in a 0.35 mum CMOS high-voltage process and occupies a chip area of 850 mum times 500 mum.