Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC
Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC
复制标题
在基于 FPGA 的 SoC 中安全地防止总线事务期间的无限延迟
DOI：
10.1109/fccm48280.2020.00026
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
G. Buttazzo
中科院分区：
文献类型：
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作者：
Francesco Restuccia;Alessandro Biondi;Mauro Marinoni;G. Buttazzo
高级可扩展接口 (AXI) 是一种开放标准通信总线接口，在大多数商用现成 FPGA 片上系统 (SoC) 中实现，用于在芯片内交换数据。不幸的是，AXI 标准没有强制要求任何机制来检测所连接模块可能存在的不当行为。这项工作表明，规范的缺乏对 AXI 总线的流行实现产生了相关影响。特别是，它展示了如何在存在行为不当的总线主控的情况下轻松地在现代 FPGA 片上系统上注入任意长的延迟。为了安全地解决这个问题，本文提出了一种通用时序分析，以限制在标称条件下定期调用的硬件加速器的执行。然后，该时序分析用于配置名为 AXI Stall Monitor (ASM) 的无延迟硬件模块，该模块也在本文中提出，能够检测并安全地解决 AXI 总线事务期间可能出现的停顿。当偏离标称条件时，ASM 为硬件加速器留下了量化的灵活性。该贡献最终得到了 Xilinx 在 Zynq-7000 和 Zynq Ultrascale+SoC 上的一组实验的支持。
Advanced eXtensible Interface (AXI) is an open-standard communication bus interface implemented in most commercial off-the-shelf FPGA System-on-Chips (SoC) to exchange data within the chip. Unfortunately, the AXI standard does not mandate any mechanism to detect possible misbehavior of the connected modules. This work shows that this lack of specification has a relevant impact on popular implementations of the AXI bus. In particular, it is shown how it is easily possible to inject arbitrarily-long delays on modern FPGA system-on-chips under the presence of misbehaving bus masters. To safely solve this issue, this paper presents a general timing analysis to bound the execution of periodically-invoked hardware accelerators in nominal conditions. This timing analysis is then used to conFigure a latency-free hardware module named AXI Stall Monitor (ASM), also proposed in this paper, capable of detecting and safely solving possible stalls during AXI bus transactions. The ASM leaves a quantified flexibility to the hardware accelerators when deviating from nominal conditions. The contribution is finally supported by a set of experiments on the Zynq-7000 and Zynq Ultrascale+SoCs by Xilinx.