Grid synchronization PLL based on cascaded delayed signal cancellation
Grid synchronization PLL based on cascaded delayed signal cancellation
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DOI：
10.1109/ecce.2010.5617996
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发表时间：
2010-11
期刊：
影响因子：
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通讯作者：
Yi Fei Wang;Y. Li
中科院分区：
文献类型：
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作者：
Yi Fei Wang;Y. Li
在分布式发电（DG）单元的电网同步过程中，锁相环（PLL）被广泛认为是检测电网相位角的有效方法。当电网电压受到不平衡和谐波污染时，DG 控制器中使用的传统 PLL 方案必须在稳态精度和瞬态动态之间进行折衷。为了同时实现良好的稳态和瞬态性能，本文提出了一种通用的延迟信号消除（DSC）算子，可以对其进行定制以消除任何指定的谐波。所提出的 DSC 算子可以进一步级联，以逐步抑制所有不需要的谐波。然后，调节后的电压信号可用于 PLL 环路，以在高控制带宽下实现快速瞬态响应，而不会受到谐波引起的稳态误差的影响。基于不同配置的 DSC 算子，开发了两种 PLL 设计，即 CDSC-PLL1 和 CDSC-PLL2。具体来说，CDSC-PLL1针对具有不平衡和奇偶谐波的电网电压，而CDSC-PLL2进一步解决不对称谐波，即由不对称失真的三相电压产生的谐波。所有提出的 PLL 设计都具有非常简单的结构并且可以轻松实现。实验结果证实了其优越的性能。
During the grid synchronization of distributed generating (DG) units, phase-locked loop (PLL) is well accepted as an efficient approach to detect grid phase angle. Conventional PLL schemes used in DG controller have to compromise between steady-state accuracy and transient dynamics when grid voltage is polluted by unbalance and harmonics. To simultaneously realize good steady-state and transient performances, this paper proposes a general delayed signal cancellation (DSC) operator, which can be tailored to eliminate any specified harmonic. The proposed DSC operator can be further cascaded to stepwisely reject all undesired harmonics. Then the conditioned voltage signal can be used in PLL loop to achieve fast transient response at high control bandwidth without suffering from the steady-state error caused by harmonics. Based on differently configured DSC operators, two PLL designs are then developed, namely CDSC-PLL1 and CDSC-PLL2. Specifically, CDSC-PLL1 is aimed for grid voltage with unbalance and odd/even harmonics, while CDSC-PLL2 further addresses asymmetrical harmonics, i.e. harmonics arising from asymmetrically distorted three-phase voltages. All proposed PLL designs have very simple structure and can be easily implemented. The superior performance is confirmed by experimental results.