Ultra thin chips for miniaturized products
Ultra thin chips for miniaturized products
复制标题
用于小型产品的超薄芯片
DOI：
10.1007/s00542-002-0264-9
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发表时间：
2001
期刊：
影响因子：
--
通讯作者：
H. Reichl
中科院分区：
文献类型：
--
作者：
E. Jung;A. Ostmann;D. Wojakowski;C. Landesberger;R. Aschenbrenner;H. Reichl
对产品小型化的需求，特别是移动应用和自主系统，正在继续推动电子产品和制造方法的发展。过去小型化发展的一个关键是使用未包装的裸片。节省了包装的体积和重量，显著减少了占地面积。进一步小型化的下一步设想是在小型化子系统上集成功能，即系统级封装（SiP），与全硅集成（片上系统，SoC）形成对比。使用最新的制造方法可以将SiP方法与体积集成相结合。到目前为止，大多数系统采用单面或双面填充系统载波。无源组件的嵌入是向前迈出的第一步。新的挑战是不仅要集成无源元件，还要集成有源电路（IC）和必要的热管理。超薄芯片（即硅模薄至总厚度约50 μm）有助于实现这些目标。这种厚度的芯片可以嵌入到现代层压板PCB的介电层中。微通孔技术允许将嵌入式芯片连接到系统电路的外表面。作为微系统集成的最终目标，可以设想光学和流体系统组件的嵌入。本文提出了将薄硅晶片嵌入聚合物体系载流子的第一种方法。重点介绍了电接触的嵌入和制造以及热管理等方面。为了达到垂直堆叠的“砖盒”型超薄（UT）封装的目标，薄硅芯片被嵌入并连接在外围UT BGA上。
The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. One key to miniaturization developed in the past was the use of unpackaged, bare dice. Saving the volume and weight of the package, significant reduction in footprint was achieved. A next step conceived to further the miniaturization is the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP), in contrast to a full silicon integration (System-on-Chip, SoC). The use of recent manufacturing methods allows to merge the SiP approach with a volumetric integration. Up to now, most of the systems utilize single- or double-sided populated system carriers. Embedding of passive components was a first step forward. A new challenge is to incorporate not only passive components, but active circuitry (IC's) and the necessary thermal management as well. Ultra thin chips (i.e. silicon dies thinned down to ∼50 μm total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB's. Micro via technology allows to connect the embedded chip to the outer faces of the system circuitry. As an ultimate goal for microsystem integration, the embedding of optical and fluidical system components can be envisioned. This paper presents the first approach to embed thin silicon dies in to polymeric system carriers. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. To reach the goal of a vertically stackable “box-of-bricks” type of ultra thin (UT) package, thin silicon chips are embedded and interconnected on a peripheral UT BGA.