A fully digital-compatible BIST strategy for ADC linearity testing
A fully digital-compatible BIST strategy for ADC linearity testing
复制标题
用于 ADC 线性测试的完全数字兼容的 BIST 策略
DOI：
10.1109/test.2007.4437655
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
R. Geiger
中科院分区：
文献类型：
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作者：
Hanqing Xing;Hanjun Jiang;Degang Chen;R. Geiger
数字测试比模拟和混合信号测试更容易和便宜，因为直接的连接和低成本的测试器。本文提出了一种完全数字兼容的内置自检策略，用于在所有数字测试环境下进行ADC线性度测试。采用片上低精度dac作为刺激发生器，具有面积小、设计简单等优点。在逻辑块的控制下，使用基于直方图的方法测试adc的非线性。所描述的策略能够以较小的硬件开销逐一表征ADC转换级别。仿真和实验结果表明，该电路和BIST策略仅使用7位线性dac就可以将12位adc的INLk误差测试到plusmn0.2 LSB精度水平。
Digital testing is much easier and cheaper than analog and mixed-signal testing because of the straightforward connections and the low-cost testers. This paper presents a fully digital-compatible built-in self-test strategy for ADC linearity testing using all digital testing environments. On-chip, low-accuracy DACs, which are area efficient and simple to design, are implemented as the stimulus generator. ADCs' nonlinearities are tested using a histogram-based method under the control of a logic block. The described strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INLk error of 12-bit ADCs to plusmn0.2 LSB accuracy level using only 7-bit linear DACs.