A time-multiplexed FPGA architecture for logic emulation
A time-multiplexed FPGA architecture for logic emulation
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用于逻辑仿真的时分复用 FPGA 架构
DOI：
10.1109/cicc.1995.518231
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发表时间：
1995
期刊：
影响因子：
--
通讯作者：
David Lewis
中科院分区：
文献类型：
--
作者：
D. Jones;David Lewis
本文提出了一种面向逻辑仿真的FPGA结构，以实现单位硅面积上最大的可用逻辑密度和快速映射。逻辑电路被转换成由处理器元件的网络顺序执行的程序。总体而言，对于给定的硅面积，与基于FPGA的逻辑仿真器相比，原始逻辑块增加了7倍，可用逻辑块增加了25倍。
This paper presents an architecture for a FPGA oriented towards logic emulation, to achieve maximum usable logic density per unit silicon area, and fast mapping. Logic circuits are translated into a program that is executed sequentially by a network of processor elements. Overall, a sevenfold increase in raw logic blocks, and a 25-fold increase in usable logic blocks compared to a FPGA-based logic emulator is expected for a given silicon area.