A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme
复制标题
用于具有选择性源线驱动方案的低能耗图像处理器的 28 nm FD-SOI 8T 双端口 SRAM
DOI：
10.1109/tcsi.2018.2885536
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发表时间：
2019
期刊：
影响因子：
--
通讯作者：
and M. Yoshimoto
中科院分区：
文献类型：
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作者：
H. Mori;T. Nakagawa;Y. Kitahara;Y. Kawamoto;K. Takagi;S. Yoshimoto;S. Izumi;H. Kawaguchi;and M. Yoshimoto
本文提出了一种采用 28 nm 全耗尽 SOI (FD-SOI) 工艺技术的低能耗 64 Kb 八晶体管 (8T) 单读/单写双端口图像存储器。我们提出的 SRAM 采用选择性源线驱动 (SSD) 方案和连续数据写入技术，以提高低电压下的主动能效。新颖的 SSD 方案控制源线电压并消除读取操作中未选定列的泄漏能量。我们采用 28 nm FD-SOI 工艺技术制造了 64 Kb 8T 双端口 SRAM。 8T SRAM 单元尺寸为 0.291 × 1.457 μm2。该测试芯片的工作电压为 0.48V，存取时间为 135ns。能量最低点是在电源电压为 0.56 V 且存取时间为 35 ns 时，写入操作中达到 265.0 fJ/周期，读取操作中达到 389.6 fJ/周期。这些因素分别比传统方案的8T双口SRAM小30%和26%。
This paper presents a low-energy 64-Kb eight-transistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 8T SRAM cell size is 0.291 × 1.457 μm2. The test chip exhibits 0.48-V operation at an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme.