Bridging the FPGA programmability-portability Gap via automatic OpenCL code generation and tuning
Bridging the FPGA programmability-portability Gap via automatic OpenCL code generation and tuning
复制标题
通过自动 OpenCL 代码生成和调整来缩小 FPGA 可编程性与可移植性之间的差距
DOI:
10.1109/asap.2016.7760796
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发表时间:
2016
期刊:
影响因子:
--
通讯作者:
Wu
中科院分区:
文献类型:
--
作者:
K. Krommydas;Ruchira Sasanka;Wu
Programming FPGAs has been an arduous task that requires extensive knowledge of hardware design languages (HDLs), such as Verilog or VHDL, and low-level hardware details. With OpenCL support for FPGAs, the design, prototyping and implementation of an FPGA is increasingly moving towards a much higher level of abstraction, when compared to the intrinsically low-level nature of HDLs. On the other hand, in the context of traditional (i.e., CPU) software development, OpenCL is still considered to be low-level and complex because the programmer needs to manually expose parallelism in the code. In this work, we present our approach to enhancing FPGA programmability via GLAF, a visual programming framework, to automatically generate synthesizable OpenCL code with an array of FPGA-specific optimizations. We find that our tool facilitates the development process and produces functionally correct and well-performing code on the FPGA for our molecular modeling, gene sequence search, and filtering algorithms.