Low Area and Low Power FPGA Implementation of a DBSCAN-Based RF Modulation Classifier
Low Area and Low Power FPGA Implementation of a DBSCAN-Based RF Modulation Classifier
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DOI：
10.1109/ojcs.2024.3355693
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发表时间：
2024
影响因子：
5.9
通讯作者：
Bill Gavin;Tiantai Deng;E. Ball
中科院分区：
文献类型：
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作者：
Bill Gavin;Tiantai Deng;E. Ball
本文提出了一种新的低面积、低功耗的现场可编程门阵列（FPGA）实现基于噪声应用的密度空间聚类（DBSCAN）算法的射频（RF）调制分类器，称为DBCLASS。所提出的体系结构通过利用并行性、定制排序算法和消除内存访问，展示了一种高效硬件实现DBSCAN算法的新方法。该设计在实验室捕获的RF数据高于8 dB信噪比（SNR）的情况下实现了100%的分类精度，同时与下一个最快的设计相比，延迟提高了7.5倍，与下一个最小的完整系统相比，使用的FPGA总资源减少了3.65倍，功耗降低了4.75倍。所提出的设计非常适合资源受限的应用，例如移动认知无线电和频谱监测系统。
This paper presents a new low-area and low-power Field Programmable Gate Array (FPGA) implementation of a Radio Frequency (RF) modulation classifier based on the Density-Based Spatial Clustering of Applications with Noise (DBSCAN) algorithm, known as DBCLASS. The proposed architecture demonstrates a novel approach for the efficient hardware realisation of the DBSCAN algorithm by utilising parallelism, a bespoke sorting algorithm, and eliminating memory access. The design achieves 100% classification accuracy with lab-captured RF data above 8 dB signal-to-noise ratio(SNR) whilst exhibiting an improvement of latency in comparison to the next quickest design by a factor of 7.5, a reduction in terms of total FPGA resources used in comparison to the next smallest complete system by a factor of 3.65, and a reduction in power consumption over the next most efficient by a factor of 4.75. The proposed design is well suited for resource-constrained applications, such as mobile cognitive radios and spectrum monitoring systems.