Register Cache System Not for Latency Reduction Purpose
Register Cache System Not for Latency Reduction Purpose
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DOI：
10.1109/micro.2010.43
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发表时间：
2010-12
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影响因子：
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通讯作者：
Ryota Shioya;Kazuo Horio;M. Goshima;S. Sakai
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作者：
Ryota Shioya;Kazuo Horio;M. Goshima;S. Sakai
寄存器高速缓存是为了解决当前超标量处理器中寄存器文件庞大的问题而提出的。寄存器缓存减少了寄存器文件的有效访问延迟，以改善IPC，简化了旁路网络，并减少了主寄存器文件的端口。虽然以前的工作的主要目的是提高IPC，寄存器缓存上的未命中可能会降低IPC。我们提出了非延迟导向的寄存器缓存系统（NORCS）。虽然NORCS的效果与传统系统相同，但它没有传统系统所遭受的寄存器高速缓存未命中惩罚。在NORCS中，寄存器高速缓存本身与传统系统没有什么不同。不同之处在于，指令流水线具有读取主寄存器文件的阶段，所有指令都要经过这些阶段，而不管寄存器缓存命中/未命中。因此，NORCS的指令流水线不会立即受到寄存器缓存未命中的干扰。对于实际的4路超标量处理器，NORCS可以将旁路网络简化为与1周期延迟寄存器文件相同的复杂度，并将主寄存器文件的端口从12个减少到4个。CACTI仿真表明，与不带寄存器缓存的基准模型相比，面积和功耗分别降低了24.9%和31.9%。虽然这些结果与传统系统没有什么不同，但IPC差异很大。由于该高速缓存未命中惩罚，传统系统的IPC降低到83.1%，而NORCS的IPC保持在98.0%。
A register cache has been proposed to solve the problems of the huge register files of recent super scalar processors. The register cache reduces the effective access latency of the register file for IPC improvement, simplifies the bypass network, and reduces the ports of the main register file. Though the primary purpose of the previous works is to improve IPC, the misses on the register cache may degrade the IPC. We propose Non-Latency-Oriented Register Cache System (NORCS). Though the effects of NORCS are the same as the conventional systems, it is free from register cache miss penalties that the conventional systems suffer from. In NORCS, the register cache itself is not different from that of the conventional systems. The difference is that the instruction pipeline has stages to read the main register file, which all instructions go through regardless of register cache hit / miss. Therefore, the instruction pipeline of NORCS is not immediately disturbed by the register cache misses. For a realistic 4-way super scalar processor, NORCS can simplify the bypass network to the same complexity as a 1-cycle-latency register file, and reduce the ports of the main register file from 12 to 4. CACTI simulation shows that the area and power consumption are reduced to 24.9% and 31.9% compared to the baseline model without register cache. Though these results are not different from the conventional systems, IPCs differ greatly. IPC of the conventional system decreases to 83.1% because of the cache miss penalties, while that of NORCS is retained at 98.0%.