Architectures for multiplierless fast Fourier transform hardware implementation in VLSI
Architectures for multiplierless fast Fourier transform hardware implementation in VLSI
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VLSI 中无乘法器快速傅立叶变换硬件实现的架构
DOI：
10.1109/tassp.1987.1165093
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发表时间：
1987
期刊：
影响因子：
--
通讯作者：
W. Perera
中科院分区：
文献类型：
--
作者：
W. Perera
本文提出了一种新的处理器的实现无乘法器FFT的超大规模集成电路。该算法方案是专门为用于这些FFT的简单二进制系数定制的，这使得乘法变得微不足道。(The所处理的系数类是具有最多2个非零数字的系数类;即，2的2次幂的总和，每个幂在0-4的范围内。）一个单片处理单元的4点DFT（基4 FFT）的执行时间为400 ns，使用10 MHz的时钟已实现。该芯片估计最大门数为11000，引脚数为85。它具有使用20个处理IC实现1024点FFT的40 MHz吞吐率的能力。使用4点芯片实现更高的基数算法和其他各种问题进行了讨论。
This paper presents a novel processor for the implementation of multiplierless FFT's in VLSI. The arithmetic scheme is specially tailored for the simple binary coefficients used for these FFT's, which make multiplication trivial. (The class of coefficients dealt with are those that have a maximum of 2 nonzero digits; i.e., sum of 2 integers powers of 2 with each power in the range 0-4.) A single chip processing element for a 4-point DFT (for a radix 4 FFT) with an execution time of 400 ns using a 10 MHz clock has been realized. The chip has an estimated maximum gate count of 11 000 and pin count of 85. It has the capability of achieving a 40 MHz throughput rate for a 1024-point FFT using 20 processing IC's. The use of the 4-point chip to implement higher radix algorithms and various other issues are discussed.