Solving Boolean Satisfiability with Dynamic Hardware Configurations

Solving Boolean Satisfiability with Dynamic Hardware Configurations
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使用动态硬件配置解决布尔可满足性

DOI:
10.1007/bfb0055260
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发表时间:
1998
期刊:
International Journal of Parallel, Emergent and Distributed Systems
影响因子:
--
通讯作者:
S. Malik
S. Malik
中科院分区:
--
文献类型:
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作者:
Peixin Zhong;M. Martonosi;P. Ashar;S. Malik

文献摘要

被引文献

相似文献

布尔值满意度(SAT)是许多重要的商业应用程序的核心计算机科学问题。 NP完整的问题是,已经提出了许多不同的加速坐在硬件或软件中的方法。特别是,我们先前的工作研究了使用可配置硬件来加速SAT来实现公式特定求解器电路的机制。尽管取得了进展,但SAT求解器运行时间仍然展示进一步改进的余地。
Boolean satisfiability (SAT) is a core computer science problem with many important commercial applications. An NP-complete problem, many different approaches for accelerating SAT either in hardware or software have been proposed. In particular, our prior work studied mechanisms for accelerating SAT using configurable hardware to implement formula-specific solver circuits. In spite of this progress, SAT solver runtimes still show room for further improvement.