A High-Frequency Three-Level Buck Converter With Real-Time Calibration and Wide Output Range for Fast-DVS
A High-Frequency Three-Level Buck Converter With Real-Time Calibration and Wide Output Range for Fast-DVS
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适用于快速 DVS 的具有实时校准和宽输出范围的高频三电平降压转换器
DOI：
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发表时间：
2018
影响因子：
5.4
通讯作者：
P. Mok
中科院分区：
文献类型：
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作者：
Xun Liu;Cheng Huang;P. Mok
本文提出了一种50 MHz的5 V输入3 W输出三电平降压变换器。提出了一种飞跨电容（<inline-formula><tex-math notation="LaTeX">$C_{F}$</tex-math></inline-formula>）的实时校准方法，以确保<inline-formula><tex-math notation="LaTeX">$C_{F}$</tex-math></inline-formula>上的恒定电压为<inline-formula><tex-math notation="LaTeX">$V_{g}$</tex-math></inline-formula>/2，该电压高度依赖于各种实际条件，如寄生电容、时间失配或来自<inline-formula><tex-math notation="LaTeX">$C_{F}$的</tex-math></inline-formula>任何负载电路。校准是必要的，以确保可靠性和最小化电感电流和输出电压涟漪，从而保持三电平操作的优点，并进一步扩展系统带宽，而不会遇到次谐波振荡。该转换器采用UMC 65 nm工艺制造，采用标准2.5 V I/O器件，能够处理5 V输入电压，并提供0.6-4.2 V宽的输出范围。在测量中，<inline-formula><tex-math notation="LaTeX">$C_{F}$</tex-math></inline-formula>两端的电压在各种条件下始终被校准为<inline-formula><tex-math notation="LaTeX">$V_{g}$</tex-math></inline-formula>/2，以释放高侧和低侧功率晶体管以及<inline-formula><tex-math notation="LaTeX">$C_{F}$上</tex-math></inline-formula>的电压应力，并确保可靠性，输出电压涟漪降低高达69%。峰值效率达90%，参考跟踪响应为23-29 ns/V。
This paper presents a 50-MHz 5-V-input 3-W-output three-level buck converter. A real-time flying capacitor (<inline-formula> <tex-math notation="LaTeX">$C_{F}$ </tex-math></inline-formula>) calibration is proposed to ensure a constant voltage of <inline-formula> <tex-math notation="LaTeX">$V_{g}$ </tex-math></inline-formula>/2 across <inline-formula> <tex-math notation="LaTeX">$C_{F}$ </tex-math></inline-formula>, which is highly dependent on various practical conditions, such as parasitic capacitance, time mismatches, or any loading circuits from <inline-formula> <tex-math notation="LaTeX">$C_{F}$ </tex-math></inline-formula>. The calibration is essential to ensure the reliability and minimize the inductor current and output voltage ripple, thus maintaining the advantages of the three-level operation and further extending the system bandwidth without encountering sub-harmonic oscillation. The converter is fabricated in a UMC 65-nm process using standard 2.5-V I/O devices, and is able to handle a 5-V input voltage and provide a 0.6–4.2-V-wide output range. In the measurement, the voltage across <inline-formula> <tex-math notation="LaTeX">$C_{F}$ </tex-math></inline-formula> is always calibrated to <inline-formula> <tex-math notation="LaTeX">$V_{g}$ </tex-math></inline-formula>/2 under various conditions to release the voltage stress on the high- and low-side power transistors and <inline-formula> <tex-math notation="LaTeX">$C_{F}$ </tex-math></inline-formula>, and to ensure reliability with up to 69% output voltage ripple reduction. A 90% peak efficiency and a 23–29-ns/V reference-tracking response are also observed.