A Terabit Readout System for the LHCb VELO Upgrade I
A Terabit Readout System for the LHCb VELO Upgrade I
复制标题
用于 LHCb VELO 升级 I 的太比特读出系统
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
P. Vázquez Regueiro
中科院分区：
文献类型：
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作者：
A. F. Prieto;P. Vázquez Regueiro
本文将描述升级后的LHCb实验的新像素顶点探测器（VELO）的高速读出挑战，该实验计划于2019/2020年安装。电子读出链的所有元件都将升级，以科普~40 MHz全事件读出速率的要求。像素传感器配备VeloPix ASIC，并放置在距离光束约5 mm处的二级真空罐中，辐射环境极高且不均匀。最高占用率的前端ASIC使用四条5.13 Gbits/s数据链路时，像素命中率将超过约800 Mhits/s。每个模块包含六个VeloPix ASIC，与两个前端混合电路焊线。这些通过非常低质量的kapton磁带连接到一个控制混合托管一个GBTx ASIC与一个4.8 Gbits/s的双向链路。使用低质量柔性带将高速信号传输到真空室的壁。定制板将信号路由到真空罐外部，一旦到达空气侧，光和电源板将电高速信号转换为光信号，以便从洞穴传输到探测器外的电子设备。
This paper will describe the high-speed readout challenge for the new pixel vertex detector (VELO) of the upgraded LHCb experiment, scheduled for installation in 2019/2020. All elements of the electronics readout chain will be upgraded to cope with the requirement of ~40 MHz full event readout rate. The pixel sensors are equipped with VeloPix ASICs and placed at ~5 mm from the beam in a secondary vacuum tank and extremely high and nonhomogeneous radiation environment. The highest occupancy front-end ASICs will have pixel-hit rates above ~800 Mhits/s using four 5.13 Gbits/s data links. Each module houses six VeloPix ASICs, wire bonded to two front-end hybrids. These are connected via very low mass kapton tapes to a control hybrid hosting one GBTx ASIC with one 4.8 Gbits/s bidirectional link. High speed signals are transmitted to the wall of the vacuum chamber using low mass flex tapes. A custom board routes the signals outside the vacuum tank and once on the air side, an Optical and Power Board converts the electrical high speed signals into optical signals for transmission from the cavern to the off-detector electronics.