Large zero bias peaks and dips in a four-terminal thin InAs-Al nanowire device-猫眼课题宝

DOI：

10.1103/physrevresearch.4.033235

发表时间：

2021-07

期刊：

Physical Review Research

影响因子：

4.2

通讯作者：

中科院分区：

文献类型：

作者：

Huading Song;Zitong Zhang;D. Pan;Dong E. Liu;Zhao-Jin Wang;Zhan-qiang Cao;Lei Liu;Lianjun Wen;Dunyuan Liao;Ran Zhuo;Dong E. Liu;Runan Shang;Jianhua Zhao;Haoqing Zhang

我们报告了一个薄的InAs-Al混合超导体-超导体纳米线器件的电子输运研究使用四端设计。与以前的工作相比，更薄的InAs纳米线（直径小于40 nm），预计将达到更少的子带制度。四端器件设计不包括电极接触电阻，电极接触电阻是一个未知值，不可避免地会影响到预先报告的器件电导。使用隧道光谱，我们发现大的零偏置峰（ZBP）在2 e 2 /h的数量级的双折射电导。通过扫描不同的栅极电压和磁场来研究ZBP的演变，我们发现了零偏置峰值和零偏置谷之间的转变，而零偏置电导接近2 e2/h。我们讨论了一个拓扑平凡的解释，涉及无序，光滑的潜在变化和准马约拉纳零模式。器件制作：InAs纳米线生长的分子束外延，然后在原位生长的Al膜。然后通过洁净室纸巾擦拭将纳米线从生长芯片转移到p掺杂Si/SiO2衬底上。在50 ° C下使用Transient Aluminum Etchant Type D选择性地蚀刻Al膜的一部分10秒，其中蚀刻窗口通过电子束光刻（EBL）图案化。在另一轮EBL中制造电接触和侧栅极。在金属沉积之前，在装载室中以50 W的功率和0.05托的压力进行40秒长的氩等离子体蚀刻以确保欧姆接触。数据分析：对于dI/dV与V和B（或栅极电压）的所有2D彩色图，基于依赖于粒子的每个数据集的对称性，估计偏置偏移V偏移（± 50 uV）并从V中减去超导间隙的空穴对称性（有关V偏移的详细信息，请参阅数据存储库）。对于颜色图，dI/dV vs V曲线被插值到规则间隔的V网格上。偏置扫描中的零偏置线切割是基于电导值来提取的，

We report electron transport studies of a thin InAs-Al hybrid semiconductor-superconductor nanowire device using a four-terminal design. Compared to previous works, thinner InAs nanowire (diameter less than 40 nm) is expected to reach fewer sub-band regime. The four-terminal device design excludes electrode contact resistance, an unknown value which has inevitably aﬀected pre-viously reported device conductance. Using tunneling spectroscopy, we ﬁnd large zero-bias peaks (ZBPs) in diﬀerential conductance on the order of 2 e 2 /h . Investigating the ZBP evolution by sweeping various gate voltages and magnetic ﬁeld, we ﬁnd a transition between a zero-bias peak and a zero-bias dip while the zero-bias conductance sticks close to 2 e 2 /h . We discuss a topologically trivial interpretation involving disorder, smooth potential variation and quasi-Majorana zero modes. Device Fabrication: The InAs nanowires were grown by molecular-beam epitaxy followed by an in-situ growth of Al film. The nanowires were then transferred from the growth chip to a p-doped Si/SiO 2 substrate by wipes of clean room tissues. Part of the Al film was selectively etched using Transene Aluminum Etchant Type D at 50 ◦ C for 10 seconds with etch windows patterned by electron-beam lithography (EBL). Electric contacts and side gates were fabricated in another round of EBL. Before metal deposition, a 40s long Argon plasma etching at a power of 50 W and pressure of 0.05 Torr was performed in the load-lock to ensure Ohmic contacts. Data Analysis: For all the 2D color maps of dI/dV vs V and B (or gate voltages), a bias offset V offset ( ∼ 50 uV) is estimated and subtracted from V , based on the symmetry of each data set which relies on the particle-hole symmetry of the superconducting gap (see data repository for V offset details). For the color-map plots, the dI/dV vs V curves are interpolated on to a regularly spaced V grid. Zero-bias line-cuts in bias scans are extracted based on the conductance value whose corresponding

Large zero bias peaks and dips in a four-terminal thin InAs-Al nanowire device

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