A Generic VHDL Template for 2D Stencil Code Applications on FPGAs
A Generic VHDL Template for 2D Stencil Code Applications on FPGAs
复制标题
用于 FPGA 上 2D 模板代码应用的通用 VHDL 模板
DOI：
10.1109/isorcw.2012.39
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
D. Fey
中科院分区：
文献类型：
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作者：
Michael Schmidt;M. Reichenbach;D. Fey
基于2D模板代码应用程序的自组织系统的有效实现，例如我们发达的行进像素算法，是一个巨大的挑战。它们是数据密集型的，也是计算密集型的，因为通常需要大量的迭代。 fPGA被预定为实现这些算法。它们非常灵活，即使在高性能版本中，也可以进行可扩展的并行处理，并具有适度的功耗。因此，FPGA具有使这些应用程序具有实时能力的高度资格。我们的目标是为FPGA中的此类操作实施有效的参数化缓冲和并行处理方案，以尽可能快地对其进行处理。我们开发了一个通用的VHDL模板，该模板允许与应用程序和硬件约束有关的2D模板代码应用程序的可扩展并行化和管道进行。
The efficient realization of self-organizing systems based on 2D stencil code applications, like our developed Marching Pixel algorithms, is a great challenge. They are data-intensive and also computational-intensive, because often a high number of iterations is required. FPGAs are predestined for the realization of these algorithms. They are very flexible, allow a scalable parallel processing and have a moderate power consumption, even in high-performance versions. Therefore, FPGAs are highly qualified to make these applications also real-time capable. Our goal was to implement an efficient parameterizable buffering and parallel processing scheme for such operations in FPGAs, to process them as fast as possible. We developed a generic VHDL template which allows a scalable parallelization and pipelining of 2D stencil code applications in relation to application and hardware constraints.