Variation-aware near threshold circuit synthesis
Variation-aware near threshold circuit synthesis
复制标题
变化感知的近阈值电路综合
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
M. Tahoori
中科院分区：
文献类型：
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作者：
M. Golanbari;S. Kiamehr;Mojtaba Ebrahimi;M. Tahoori
近阈值计算（NTC）被证明是一种很有前途的方法来提高VLSI电路的能量效率。然而，通过降低电源电压，工艺变化的延迟影响显着增加，导致与标称电压相比，性能变化高达20倍。因此，通过增加时间裕度来处理这种变化是对能量和性能的浪费，这在标称电压中很常见。因此，在近阈值电路设计阶段考虑工艺变化的影响是至关重要的。在本文中，我们提出了一个变化感知的NTC合成流程来解决这个问题。目标是通过考虑统计变化信息，在设计期间提高电路的性能和能量效率。这是通过向合成工具提供变化信息，通过统计静态时序分析（SSTA）评估合成电路的性能，并以迭代的方式相应地调整时序约束来完成的。一组基准电路的仿真结果表明，本文提出的流减少了86.6%的变化，性能和能量分别提高了24.9%和7.4%，面积开销分别为4.8%。
Near-Threshold Computing (NTC) is shown to be a promising approach for improving the energy efficiency of VLSI circuits. Nevertheless, by reducing the supply voltage the delay impact of process variation significantly increases, leading to up to 20× performance variation compared to the nominal voltage. As a result, it is wasteful of energy and performance to deal with such variation by increasing the timing margins, which is common in nominal voltage. Therefore, considering the impact of process variation during the near-threshold circuit design phase is of decisive importance. In this paper, we propose a variation-aware synthesis flow for NTC to address this problem. The objective is to improve the performance and energy efficiency of a circuit during design time by considering statistical variation information. This is done by providing variation information to the synthesis tool, evaluating the performance of the synthesized circuit by Statistical Static Timing Analysis (SSTA), and adjusting the timing constraints accordingly in an iterative manner. Simulation results for a set of benchmark circuits show that our proposed flow reduces the variation by 86.6% and improves the performance and energy by 24.9% and 7.4%, respectively, at the expense of 4.8% area overhead.