Latch susceptibility to transient faults and new hardening approach

Latch susceptibility to transient faults and new hardening approach
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DOI:
10.1109/tc.2007.1070
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发表时间:
2007-09-01
影响因子:
3.7
通讯作者:
Metra, Cecilia
Metra, Cecilia
中科院分区:
计算机科学2区
文献类型:
--
作者:
Omana, Martin;Rossi, Daniele;Metra, Cecilia

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本文分析了影响传统锁存结构节点的暂态故障产生输出软错误的条件。我们调查了所有锁存节点对TF的敏感性,并确定了最关键的一个(S)。我们发现,对于使用背靠背反相器进行正反馈的标准锁存器,其反馈路径中的内部节点是最关键的。这种节点在下文中将被称为内部反馈节点。基于这一分析,我们首先提出了一种低成本的硬化锁存器,与其他硬化解决方案相比,它能够完全过滤掉影响其内部反馈节点的TF,同时呈现出对其他内部节点上的TF的较低敏感性。这是以降低对影响输出节点的TF的稳健性为代价实现的。为了克服这一可能的限制(特别是对于高可靠性应用的系统),我们提出了另一种版本的锁存器,与第一种解决方案相比,这种锁存器以较小的面积和更高的功耗为代价,也提高了输出节点的稳健性,这可能高于替代强化解决方案。此外,这两种建议的锁存器都提供了与替代解决方案相当或更高的输入节点稳健性,并提供了比经典实现和替代强化解决方案更低或相当的功率延迟乘积和面积开销。
In this paper, we analyze the conditions making transient faults (TFs) affecting the nodes of conventional latch structures generate output soft errors (SEs). We investigate the susceptibility to TFs of all latch nodes and identify the most critical one(s). We show that, for standard latches using back-to-back inverters for their positive feedback, the internal nodes within their feedback path are the most critical. Such nodes will be hereafter referred to as internal feedback nodes. Based on this analysis, we first propose a low-cost hardened latch that, compared to alternative hardened solutions, is able to completely filter out TFs affecting its internal feedback nodes while presenting a lower susceptibility to TFs on the other internal nodes. This is achieved at the cost of a reduced robustness to TFs affecting the output node. To overcome this possible limitation (especially for systems for high-reliability applications), we propose another version of our latch that, at the cost of a small area and power consumption increase compared to our first solution, also improves the robustness of the output node, which can be higher than that of alternative hardened solutions. Additionally, both proposed latches present a comparable or higher robustness of the input node than alternative solutions and provide a lower or comparable power-delay product and area overhead than classical implementations and alternative hardened solutions.