A Current Reuse Quadrature GPS Receiver in 0.13 $\mu$m CMOS
A Current Reuse Quadrature GPS Receiver in 0.13 $\mu$m CMOS
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DOI：
10.1109/jssc.2009.2039272
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发表时间：
2010-03
影响因子：
5.4
通讯作者：
Kuang-Wei Cheng;K. Natarajan;D. Allstot
中科院分区：
文献类型：
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作者：
Kuang-Wei Cheng;K. Natarajan;D. Allstot
A fully-integrated quadrature low-IF L1-band GPS receiver consumes only 6.4 mW in 0.13 μm CMOS. The RF front-end features a gate-modulated quadrature VCO for low phase noise and accurate quadrature phase signal generation. It merges the LNA, quadrature mixer, and quadrature VCO in a single current-reuse stacked topology that provides a conversion gain 42.5 dB with a power consumption of 1 mW. A continuous-time (CT) quadrature bandpass sigma-delta analog-to-digital converter (ADC) provides inherent anti-alias filtering, which simplifies the overall system. The second-order CT ΣΔ ADC achieves 65 dB dynamic range and dissipates only 4.2 mW using resistor DAC feedback. The receiver exhibits an NF of 6.5 dB and an IIP3 of - 30 dBm; the PLL phase noise is -110 dBc/Hz @ 1 MHz frequency offset with quadrature error less than 1°.
