6.6 A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS
6.6 A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS
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6.6 A 128Gb/s 1.3pJ/b PAM-4 发送器，采用 14nm CMOS 封装，具有可重新配置的 3-Tap FFE
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
M. Meghelli
中科院分区：
文献类型：
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作者：
Z. Deniz;J. Proesel;J. Bulzacchelli;H. Ainspan;T. Dickson;Michael P. Beakes;M. Meghelli
对更高带宽的不断增长的需求继续推动了对更快、更省电的IO的需求，使用PAM-4信令的下一代高速串行链路预计将达到高于112 Gb/S的数据速率[1-3]。虽然PAM-4的频谱效率高于NRZ，但它对残留码间干扰和噪声的耐受性较差。因此，需要具有高带宽和大输出幅度的驱动器。本文介绍了一种64 Gbaud的PAM-4 TX，它具有完全可重构的3抽头FFE，在PAM-4模式下的功率效率为1.3pJ/b，在NRZ模式下的功率效率为2.7pJ/b，差分输出摆幅为1mathm{V}{ppd}$。FFE结构的一个特点是在3个抽头之间使用完全可重新分配的FFE段，这样可以减少段的数量，从而实现更低的电容和更高的驱动器带宽。为了最大限度地降低功耗，采用了四分之一速率时钟结构和无尾4：1多路复用器，该多路复用器也充当无尾CML输出驱动器的前置驱动器。
The ever-increasing demand for higher bandwidth continues to fuel the need for faster and more power-efficient IOs, with the next generation high-speed serial links expected to reach data rates higher than 112Gb/s using PAM-4 signaling [1–3]. While PAM-4 spectral efficiency is better than that of NRZ, it is less tolerant of residual ISI and noise. As a consequence, a driver with high bandwidth and large output amplitude is required. This paper presents a 64Gbaud PAM-4 TX with a fully reconfigurable 3-tap FFE, which achieves a power efficiency of 1.3pJ/b in PAM-4 mode and 2.7pJ/b in NRZ mode for a differential output swing of $1mathrm{V}_{ppd}$. A feature of the FFE construction is the use of fully re-assignable FFE segments among the 3 taps, which allows a reduced number of segments for lower capacitance and higher driver bandwidth. To minimize power consumption, a quarter-rate clocking architecture is adopted with a tailless 4:1 multiplexer, which also acts as a pre-driver to a tailless CML output driver.