Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics
Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics
复制标题
节能可重构 SRAM：通过数据统计降低读取功率
DOI：
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发表时间：
2017
影响因子：
5.4
通讯作者：
A. Chandrakasan
中科院分区：
文献类型：
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作者：
Chuhong Duan;Andreas J. Gotterba;M. Sinangil;A. Chandrakasan
本文介绍了一个框架，用于设计数据相关的SRAM利用统计依赖性存在于二进制值处理和存储在中间阶段的各种算法。为了证明该框架，一个可重构的条件预充电（CP）SRAM设计在一个28纳米的全耗尽绝缘体上硅CMOS工艺。为了降低读取功耗，SRAM随着数据统计的演变而重新配置其每列的预测方案。一个10 T的位单元，预测为基础的CP电路，和一个紧凑的列电路实现在一个16 kbit的SRAM测试芯片表现出63%，50%，和高达69%的应用稀疏快速傅立叶变换，目标检测和运动估计，分别与类似的存储器与朴素的预测相比，节能。还提供了分析工具的最佳预测选择所提出的低功耗存储器类。
This paper introduces a framework for designing data-dependent SRAMs taking advantage of statistical dependencies present in the binary values processed and stored in the intermediary stages of various algorithms. To demonstrate the framework, a reconfigurable conditional precharge (CP) SRAM is designed in a 28-nm fully-depleted silicon-on-insulator CMOS process. To reduce read power consumption, the SRAM reconfigures its prediction scheme for each column as the data statistics evolve. A 10T bit cell, a prediction-based CP circuit, and a compact column circuit implemented in a 16-kbit SRAM test chip demonstrate the power savings of 63%, 50%, and up to 69% for the applications sparse fast Fourier transform, object detection, and motion estimation, respectively, as compared with similar memories with naive prediction. Analysis tools for optimal prediction selection for the presented class of low-power memories are also provided.