A quasi-analytical SET model for few electron circuit simulation
A quasi-analytical SET model for few electron circuit simulation
复制标题
一种用于少电子电路仿真的准解析SET模型
DOI：
10.1109/led.2002.1004237
复制
发表时间：
2002
影响因子：
4.9
通讯作者：
K. Banerjee
中科院分区：
文献类型：
--
作者：
S. Mahapatra;A. Ionescu;K. Banerjee
提出了一种新的单电子晶体管（SETS）准解析模型，并通过与蒙特卡罗（MC）模拟的漏极电流和跨导比较验证了该模型的正确性。新方法是基于对漏极电流的隧道和热分量的单独建模，并在20多年的温度下得到验证。模型参数是物理参数，并报道了相关参数提取过程。结果表明，该模型在静态和动态状态下都能准确地模拟SET逻辑电路，并对混合（SET- cmos）电路的联合仿真具有吸引力。
A novel quasi-analytical model for single electron transistors (SETS) is proposed and validated by comparison with Monte-Carlo (MC) simulations in terms of drain current and transconductance. The new approach is based on the separate modeling of the tunneling and thermal components of the drain current, and verified over two decades of temperature. The model parameters are physical and an associated parameter extraction procedure is also reported. The model is shown to be accurate for SET logic circuit simulation in both static and dynamic regimes and is attractive for hybrid (SET-CMOS) circuit co-simulation.