A VLSI architecture for advanced video coding motion estimation
A VLSI architecture for advanced video coding motion estimation
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用于高级视频编码运动估计的 VLSI 架构
DOI：
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发表时间：
2003
期刊：
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通讯作者：
J. McCanny
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文献类型：
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作者：
S. Y. Yap;J. McCanny
随着MPEG-4 Part-10和H.264/H.26L等新视频标准的出现，对高级视频编码（AVC）的需求不断增加，特别是在可变块搜索运动估计（VBSME）领域。这导致了对合适的灵活硬件架构的研究，以执行各种类型的VBSME。提出了一种新的全搜索可变块大小运动估计（FSVBSME）的1-D VLSI结构。通过重用较小子块计算的结果来执行可变块大小、绝对差和（SAD）计算。通过在每个处理元件（PE）内结合混洗机制来排列和组合这些。传统的1-D结构只能处理一个运动矢量，而这种结构可以在相当数量的时钟周期内处理多达41个运动矢量（MV）子块（在宏块内）。
With the advent of new video standards such as MPEG-4 part-10 and H.264/H.26L, demands for advanced video coding (AVC), particularly in area of variable block searching motion estimation (VBSME), are increasing. This has led to research into suitable flexible hardware architectures to perform the various types of VBSME. We propose a new 1-D VLSI architecture for full search variable block size motion estimation (FSVBSME). The variable block size, sum of absolute differences (SAD) computation is performed by reusing the results of smaller subblock computations. These are permuted and combined by incorporating a shuffling mechanism within each processing element (PE). Whereas a conventional 1-D architecture can process only one motion vector, this architecture can process up to 41 motion vector (MV) subblocks (within a macroblock) in a comparable number of clock cycles.