A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS
A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS
复制标题
采用 65nm CMOS 集成多相 LO 生成的 24GHz 次谐波接收器前端
DOI：
10.1109/isscc.2008.4523134
复制
发表时间：
2008
期刊：
影响因子：
--
通讯作者：
F. Svelto
中科院分区：
文献类型：
--
作者：
A. Mazzanti;M. Sosio;M. Repossi;F. Svelto
标准CMOS实现的性能已被证明足以达到60 GHz的范围，甚至超过60 GHz的操作块的例子已经提出。尽管如此，接收器架构的选择需要几个特殊的考虑，以实现一个强大的低功耗解决方案。另一方面，在高频处，为了节省VCO和分频器中的功率，期望合成低于接收频率的参考频率。作者提出了一种半谐波24 GHz直接转换I/Q接收机前端，集成多相LO产生在65 nm CMOS。实验表明，足够的性能是在一个紧凑的（2.1平方毫米）低功耗（低于100毫瓦）的解决方案，在超规模的RF CMOS工艺。
Performance of standard CMOS implementations has proved sufficient up to 60 GHz range and examples of operating blocks even beyond 60 GHz have been presented. Still, the choice of the receiver architecture entails several peculiar considerations in order to achieve a robust low-power solution. On the other hand, at high frequencies, to save power in both the VCO and dividers, it is desirable to synthesize a reference frequency that is lower than the received frequency. The authors have proposed a half-harmonic 24 GHz direct-conversion I/Q-receiver front-end with integrated multi-phase LO generation in 65 nm CMOS. Experiments show that adequate performance is achieved in a compact (2.1 mm2) low-power (below 100 mW) solution in an ultra- scaled RF CMOS process.