Area-Efficient Bevel-Edge Termination Techniques for SiC High-Voltage Devices
Area-Efficient Bevel-Edge Termination Techniques for SiC High-Voltage Devices
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DOI：
10.1109/ted.2016.2532602
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发表时间：
2016-04-01
影响因子：
3.1
通讯作者：
Huang, Alex Q.
中科院分区：
文献类型：
--
作者：
Sung, Woongje;Baliga, B. Jayant;Huang, Alex Q.
综述了碳化硅（SiC）功率器件的斜边终端技术，包括斜边结终端延伸（JTE）、连续斜边终端、斜边辅助JTE和正斜边终端。所提出的斜面边缘终端技术显着降低了SiC功率器件的芯片尺寸。制作了PiN二极管和测试结构，以量化所提出的结构的相对性能。定量比较芯片尺寸减小，工艺方案，和未来的研究方向进行了详细讨论。
This paper reviews the bevel-edge termination techniques for silicon carbide (SiC) power devices, such as bevel junction termination extension (JTE), resistive-bevel termination, bevel-assisted JTE, and positive-bevel termination. The proposed bevel-edge termination techniques significantly reduce the chip size for SiC power devices. PiN diodes and test structures were fabricated to quantify the relative performance of the proposed structures. Quantitative comparison in chip size reduction, process schemes, and future research directions is discussed in detail.