A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V
A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V
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DOI：
10.1109/jssc.2012.2206683
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发表时间：
2012-10-01
影响因子：
5.4
通讯作者：
Sylvester, Dennis
中科院分区：
文献类型：
--
作者：
Seok, Mingoo;Kim, Gyouho;Sylvester, Dennis
生物医学植入物、基础设施监控系统和军事监视单元等传感系统分别在待机和活动模式下仅消耗皮瓦到千瓦。这种紧凑的功耗预算对系统中的所有构建块都有极低的功耗要求。这项工作提出了一个电压基准，用于在这样的超低功耗系统，称为2 T电压基准，这已被证明在硅跨三个CMOS技术。0.13 μ m的原型芯片显示出16.9 ppm/摄氏度（最佳）的温度系数和0.033%/V的线灵敏度，而在1350 μ m（2）中消耗2.22 pW。最低功能V为0.5 V。与其他高电压基准相比，该设计将能效提高了2至3个数量级，同时在更小的面积内表现出更好的线路灵敏度和温度系数。对于工艺扩展分析，在两次运行中测量了49个管芯，表明该设计在TC和输出电压方面表现出与文献中现有电压参考相当的扩展。演示了数字微调，并通过两个温度点微调的初始样本指导辅助一个温度点的数字微调，使TC < 50 ppm/摄氏度和+/- 0.35%的输出精度在所有25个芯片。易于技术的便携性证明与硅测量结果在65纳米，0.13微米，0.18微米CMOS技术。
Sensing systems such as biomedical implants, infrastructure monitoring systems, and military surveillance units are constrained to consume only picowatts to nanowatts in standby and active mode, respectively. This tight power budget places ultra-low power demands on all building blocks in the systems. This work proposes a voltage reference for use in such ultra-low power systems, referred to as the 2T voltage reference, which has been demonstrated in silicon across three CMOS technologies. Prototype chips in 0.13 mu m show a temperature coefficient of 16.9 ppm/degrees C (best) and line sensitivity of 0.033%/V, while consuming 2.22 pW in 1350 mu m(2). The lowest functional V is 0.5 V. The proposed design improves energy efficiency by 2 to 3 orders of magnitude while exhibiting better line sensitivity and temperature coefficient in less area, compared to other nanowatt voltage references. For process spread analysis, 49 dies are measured across two runs, showing the design exhibits comparable spreads in TC and output voltage to existing voltage references in the literature. Digital trimming is demonstrated, and assisted one temperature point digital trimming, guided by initial samples with two temperature point trimming, enables TC < 50 ppm/degrees C and +/- 0.35% output precision across all 25 dies. Ease of technology portability is demonstrated with silicon measurement results in 65 nm, 0.13 mu m, and 0.18 mu m CMOS technologies.