A Lightweight Isolation Mechanism for Secure Branch Predictors
A Lightweight Isolation Mechanism for Secure Branch Predictors
复制标题
安全分支预测器的轻量级隔离机制
DOI：
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复制
发表时间：
2020
期刊：
影响因子：
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通讯作者：
Dan Meng
中科院分区：
文献类型：
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作者：
Lutan Zhao;Peinan Li;Rui Hou;Michael C. Huang;Jiazhen Li;Lixin Zhang;Xuehai Qian;Dan Meng
最近暴露的漏洞表明，不同进程共享的分支预测器为攻击者提供了恶意训练和感知的机会。我们希望通过使用随机化的一些轻量级处理来实现这些硬件表中内容的隔离，而不是基于刷新或物理隔离的硬件资源，如下所示。 (1)内容编码。我们建议使用基于硬件的线程私有随机数来对分支预测器表的内容进行编码。它实现了类似的逻辑隔离效果，但在空间或时间开销方面几乎没有增加。 (2)索引编码。我们提出了分支预测器的随机索引机制。这破坏了分支指令地址和分支预测器条目之间的对应关系，从而增加了恶意感知攻击的噪声。我们使用基于 FPGA 的 RISC-V 处理器原型和附加辅助仿真进行的分析表明，所提出的机制在提供强大保护的同时，性能成本非常小。
Recently exposed vulnerabilities reveal that branch predictors shared by different processes leave the attackers with the opportunities for malicious training and perception. Instead of flush-based or physical isolation of hardware resources, we want to achieve isolation of the content in these hardware tables with some lightweight processing using randomization as follows. (1) Content encoding. We propose to use hardware-based thread-private random numbers to encode the contents of the branch predictor tables. It achieves a similar effect of logical isolation but adds little in terms of space or time overheads. (2) Index encoding. We propose a randomized index mechanism of the branch predictor. This disrupts the correspondence between the branch instruction address and the branch predictor entry, thus increases the noise for malicious perception attacks. Our analyses using an FPGA-based RISC-V processor prototype and additional auxiliary simulations suggest that the proposed mechanisms incur a very small performance cost while providing strong protection.
DOI：
10.1109/isca45697.2020.00022
发表时间：
2019-11
期刊：
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)
影响因子：
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作者：
S. Ainsworth;Timothy M. Jones
通讯作者：
S. Ainsworth;Timothy M. Jones