Wafer-scale silicon photonic switches beyond die size limit
Wafer-scale silicon photonic switches beyond die size limit
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DOI：
10.1364/optica.6.000490
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发表时间：
2019-04-20
期刊：
影响因子：
10.4
通讯作者：
Wu, Ming C.
中科院分区：
文献类型：
--
作者：
Seok, Tae Joon;Kwon, Kyungmok;Wu, Ming C.
快速光开关已经被提出作为一种有前途的替代方案，以使数据中心能够随着规模和数据速率的增加而持续扩展。硅光子学是一个引人注目的大规模集成光子交换机平台，利用先进的电子集成电路制造厂。在过去的十年中，硅光子交换机的端口数稳步增加到128 x 128。开关的进一步缩放受到光刻工具的最大掩模版尺寸（2- 3cm）的限制。在这里，我们建议使用晶圆级集成，以克服芯片尺寸的限制。作为概念验证演示，我们通过光刻拼接跨越掩模版边界的相同80 x 80开关块的3 x 3阵列来制造240 x 240开关。通过将波导宽度逐渐减小到10 μ m，拼接损耗显著减小（0.004dB）。在4 cm × 4 cm芯片上制作的开关具有9.8 dB的最大片上损耗，70 dB的开/关比，和小于400 ns的开关时间。据我们所知，这是有史以来报道的最大的集成光子交换机。损耗端口计数比（0.04 dB/端口）也是最低的。(C)根据OSA开放获取出版协议的条款，2019年美国光学学会
Fast optical switches have been proposed as a promising alternative to enable continual scaling of data centers with increasing size and data rates. Silicon photonics is a compelling platform for large-scale integrated photonic switches, leveraging advanced manufacturing foundries for electronic integrated circuits. In the past decade, the port counts of silicon photonic switches have increased steadily to 128 x 128. Further scaling of the switch is constrained by the maximum reticle size (2-3 cm) of lithography tools. Here, we propose to use wafer-scale integration to overcome the die size limit. As a proof of concept demonstration, we fabricated a 240 x 240 switch by lithographically stitching a 3 x 3 array of identical 80 x 80 switch blocks across reticle boundaries. Stitching loss is substantially reduced (0.004 dB) by tapering the waveguide width to 10 mu m. The fabricated switch on a 4 cm x 4 cm chip exhibits a maximum on-chip loss of 9.8 dB, an ON/OFF ratio of 70 dB, and switching times of less than 400 ns. To our knowledge, this is the largest integrated photonic switch ever reported. The loss-to-port count ratio (0.04 dB/port) is also the lowest. (C) 2019 Optical Society of America under the terms of the OSA Open Access Publishing Agreement