Scheduling designs into a time-multiplexed FPGA
Scheduling designs into a time-multiplexed FPGA
复制标题
将设计调度到时分复用 FPGA 中
DOI:
10.1145/275107.275135
复制
发表时间:
1998
期刊:
影响因子:
--
通讯作者:
S. Trimberger
中科院分区:
文献类型:
--
作者:
S. Trimberger
An algorithm is presented for partitioning a design in time. The algorithm devides a large, technology-mapped design into multiple configurations of a time-multiplexed FPGA. These configurations are rapidly executed in the FPGA to emulate the large design. The tool includes facilities for optimizing the partitioning to improve routability, for fitting the design into more configurations than the depth of the critical path and for compressing the critical path of the design into fewer configurations, both to fit the design into the device and to improve performance. Scheduling results are shown for mapping designs into an 8-configuration time-multiplexed FPGA and for architecture investigation for a time-multiplexed FPGA.
DOI:
--
发表时间:
2008
期刊:
社会保険旬報 2008年11月1日号
影响因子:
--
作者:
姫野順一;北川勝彦;高橋泰
通讯作者:
高橋泰