Low complexity bit-parallel multiplier for GF(2/sup m/) defined by all-one polynomials using redundant representation
Low complexity bit-parallel multiplier for GF(2/sup m/) defined by all-one polynomials using redundant representation
复制标题
DOI：
10.1109/tc.2005.199
复制
发表时间：
2005-12
影响因子：
3.7
通讯作者：
Ku-Young Chang;Dowon Hong;Hyunsook Cho
中科院分区：
文献类型：
--
作者：
Ku-Young Chang;Dowon Hong;Hyunsook Cho
本文介绍了一个由不可还原的全能多项式定义的有限场GF（2/sup m/）的新的位平行乘数。为了降低乘数的复杂性，我们引入了冗余表示，并使用Karatsuba提出的众所周知的乘法方法。主要思想是结合冗余表示形式和Karatsuba方法，以设计有效的位平行乘数。结果，所提出的乘数需要使用全单位多项式的先前提出的乘数少约25％和/XOR门，而它的时间延迟几乎与先前提议的时间延迟相同。
This paper presents a new bit-parallel multiplier for the finite field GF(2/sup m/) defined by an irreducible all-one polynomial. In order to reduce the complexity of the multiplier, we introduce a redundant representation and use the well-known multiplication method proposed by Karatsuba. The main idea is to combine the redundant representation and the Karatsuba method to design an efficient bit-parallel multiplier. As a result, the proposed multiplier requires about 25 percent fewer AND/XOR gates than the previously proposed multipliers using an all-one polynomial, while it has almost the same time delay as the previously proposed ones.