Large monolithic particle pixel-detector in high-voltage CMOS technology
Large monolithic particle pixel-detector in high-voltage CMOS technology
复制标题
采用高压 CMOS 技术的大型单片粒子像素探测器
DOI：
10.1016/j.nima.2010.03.161
复制
发表时间：
2010
影响因子：
1.4
通讯作者：
C. Takács
中科院分区：
文献类型：
--
作者：
I. Perić;C. Takács
本文介绍了一种采用0.35μm高压CMOS工艺实现的单片大尺寸粒子探测器。该探测器采用高压n阱/p衬底二极管作为像素传感器。二极管可以在大于60 V的情况下被反向偏置。通过这种方式，形成约10μm厚的耗尽区，在那里可以通过漂移收集信号电荷。由于在强电场区域中的快速电荷收集，预期传感器的辐射耐受性比标准MAPS探测器的情况更高。简单的像素读出电子器件在n阱内部实现。读出是基于一个选择和两个复位晶体管的源极跟随器。由于在收集电极（n阱）内部嵌入像素读出电子器件，所以在像素矩阵内不存在不敏感区。探测器芯片包含一个128×128矩阵，由21×21μm2大小的像素组成。一个选定像素行的二极管电压在矩阵底部由128个8位单斜率ADC接收。所有ADC均并行工作。ADC代码通过8个LVDS 500 MBit/s输出链路读取。读出电子器件的设计允许在不到50μs的时间内读出整个像素矩阵。芯片的总直流功耗为50 mW。芯片的所有模拟部分都采用抗辐射布局技术实现。实验结果将被提交。
A large monolithic particle pixel-detector implemented as system on a chip in a high-voltage 0.35μm CMOS technology will be presented. The detector uses high-voltage n-well/p-substrate diodes as pixel-sensors. The diodes can be reversely biased with more than 60V. In this way, depleted zones of about 10μm thickness are formed, where the signal charges can be collected by drift. Due to fast charge collection in the strong electric-field zones, a higher radiation tolerance of the sensor is expected than in the case of the standard MAPS detectors. Simple pixel-readout electronics are implemented inside the n-wells. The readout is based on a source follower with one select- and two reset-transistors. Due to embedding of the pixel-readout electronics inside the collecting electrodes (n-wells) there are no insensitive zones within the pixel matrix. The detector chip contains a 128×128 matrix consisting of pixels of 21×21μm2-size. The diode voltages of one selected pixel-row are received at the bottom of the matrix by 128 eight-bit single-slope ADCs. All ADCs operate in parallel. The ADC codes are read out using eight LVDS 500MBit/s output links. The readout electronics are designed to allow the readout of the whole pixel matrix in less than 50μs. The total DC power consumption of the chip is 50mW. All analog parts of the chip are implemented using radiation-hard layout techniques. Experimental results will be presented.