Arithmetic core generation using bit heaps
Arithmetic core generation using bit heaps
复制标题
使用位堆生成算术核心
DOI：
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
Bogdan Popa
中科院分区：
文献类型：
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作者：
Nicolas Brunie;F. D. Dinechin;Matei Iştoan;Guillaume Sergent;Kinga Illyes;Bogdan Popa
位堆是一种数据结构，它保存任意数量的位的未计算总和，每个位都以2的某个幂加权。大多数高级算术核心可以被视为涉及一个或多个位堆。我们在这里声称，这种观点导致了在代数级别、电路级别和软件工程方面的更好的全局优化。为了说明这一点，引入了一个用于定义和优化位堆的通用软件框架。该框架是在开源的FloPoCo算术核生成器中开发的，目标是支持数字信号处理器的现场可编程门阵列。它的通用性在几个例子上得到了证明：乘法器、复数乘法器、多项式和离散余弦变换。
A bit heap is a data structure that holds the unevaluated sum of an arbitrary number of bits, each weighted by some power of two. Most advanced arithmetic cores can be viewed as involving one or several bit heaps. We claim here that this point of view leads to better global optimization at the algebraic level, at the circuit level, and in terms of software engineering. To demonstrate it, a generic software framework is introduced for the definition and optimization of bit heaps. This framework, targeting DSP-enabled FPGAs, is developed within the open-source FloPoCo arithmetic core generator. Its versatility is demonstrated on several examples: multipliers, complex multipliers, polynomials, and discrete cosine transform.