A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC
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DOI：
10.1109/jssc.2014.2385753
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发表时间：
2015-01
影响因子：
5.4
通讯作者：
Ahmed Elkholy;Tejasvi Anand;Woo-Seok Choi;A. Elshazly;P. Hanumolu
中科院分区：
文献类型：
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作者：
Ahmed Elkholy;Tejasvi Anand;Woo-Seok Choi;A. Elshazly;P. Hanumolu
提出了一种采用高分辨率TDC和真Δ π小数分频器实现宽带低带内噪声的数字小数N分频PLL。小数分频器采用数字时间转换器（DTC）消除时域中的Δ T量化噪声，从而降低TDC动态范围要求。建议的数字架构采用了一个窄范围的低功耗的时间放大器为基础的TDC（TA-TDC），以实现次1 ps的分辨率。通过使用TA-TDC代替BBPD，困扰BB-PLL的极限环行为被TA-TDC极大地抑制，从而允许宽PLL带宽。所提出的架构也不太容易受到DTC的非线性，并具有更快的建立和跟踪行为相比，BB-PLL。该锁相环采用65 nm CMOS工艺制造，在50 MHz基准电压下，在4.5 GHz输出频率下，其带内噪声优于-106 dBc/Hz，锁相环带宽优于3 MHz。PLL功耗为3.7 mW，集成抖动优于490 fsrms。这意味着FoMJ为-240.5 dB，是所报告的小数N分频PLL中最好的。
A digital fractional-N PLL that employs a high resolution TDC and a truly ΔΣ fractional divider to achieve low in-band noise with a wide bandwidth is presented. The fractional divider employs a digital-to-time converter (DTC) to cancel out ΔΣ quantization noise in time domain, thus alleviating TDC dynamic range requirements. The proposed digital architecture adopts a narrow range low-power time-amplifier based TDC (TA-TDC) to achieve sub 1 ps resolution. By using TA-TDC in place of a BBPD, the limit cycle behavior that plagues BB-PLLs is greatly suppressed by the TA-TDC, thus permitting wide PLL bandwidth. The proposed architecture is also less susceptible to DTC nonlinearity and has faster settling and tracking behavior compared to a BB-PLL. Fabricated in 65 nm CMOS process, the prototype PLL achieves better than -106 dBc/Hz in-band noise and 3 MHz PLL bandwidth at 4.5 GHz output frequency using 50 MHz reference. The PLL consumes 3.7 mW and achieves better than 490 fsrms integrated jitter. This translates to a FoMJ of -240.5 dB, which is the best among the reported fractional-N PLLs.