DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing
DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing
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DOI：
10.1109/tc.2015.2512863
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发表时间：
2016-10
影响因子：
3.7
通讯作者：
Wongyu Shin;Jungwhan Choi;Jaemin Jang;Jinwoong Suh;Youngsuk Moon;Yongkee Kwon;L. Kim
中科院分区：
文献类型：
--
作者：
Wongyu Shin;Jungwhan Choi;Jaemin Jang;Jinwoong Suh;Youngsuk Moon;Yongkee Kwon;L. Kim
众所周知，相对较长的 DRAM 延迟形成了计算系统的瓶颈。然而，由于额外的制造成本，DRAM 供应商非常不愿意降低 DRAM 延迟。因此，我们的目标是在不对现有 DRAM 结构进行任何修改的情况下减少 DRAM 延迟。为了实现我们的目标，我们专注于 DRAM 的固有现象：DRAM 单元电容器中的电荷变化。然后，我们得出两个关键见解：i) 行的 DRAM 行访问延迟是自上次刷新该行以来经过的时间的函数，ii) 行的 DRAM 行访问延迟也是直到下一次刷新该行为止的剩余时间的函数。基于这两个见解，我们提出了两种减少 DRAM 延迟的机制：NUAT-1 和 NUAT-2。 NUAT-1 利用第一个关键见解，NUAT-2 利用第二个关键见解。为了进行评估，执行了电路级和系统级仿真，显示了各种环境下的性能改进。
It is widely known that relatively long DRAM latency forms a bottleneck in computing systems. However, DRAM vendors are strongly reluctant to decrease DRAM latency due to the additional manufacturing cost. Therefore, we set our goal to reduce DRAM latency without any modification in the existing DRAM structure. To accomplish our goal, we focus on an intrinsic phenomenon in DRAM: electric charge variation in DRAM cell capacitors. Then, we draw two key insights: i) DRAM row-access latency of a row is a function of the elapsed time from when the row was last refreshed, and ii) DRAM row-access latency of a row is also a function of the remaining time until the row is next refreshed. Based on these two insights, we propose two mechanisms to reduce DRAM latency: NUAT-1 and NUAT-2. NUAT-1 exploits the first key insight and NUAT-2 exploits the second key insight. For evaluation, circuit- and system-level simulations are performed, which show the performance improvement for various environments.