Redundant Logic Insertion and Latency Reduction in Self-Timed Adders
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders
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DOI：
10.1155/2012/575389
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
P. Balasubramanian;D. A. Edwards;W. Toms
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文献类型：
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作者：
P. Balasubramanian;D. A. Edwards;W. Toms
提出了一种逻辑冗余插入的新概念，它能显著降低自定时加法器电路的延迟。所提出的概念是通用的，在这个意义上，它可以扩展到各种自定时的设计方法。冗余逻辑可以被合并以生成迭代逻辑规范的高效自定时实现。基于一个32位自定时进位纹波加法器的案例研究，已经发现，冗余实现最小化的数据路径延迟的21.1%，在面积和功耗增加的2.3%和0.8%，平均相比，他们的nonredundant同行的费用。然而，当考虑进一步的窥视孔逻辑优化时，在特定场景中已经观察到延迟减少可以高达31%，同时仅伴随着分别为0.6%和1.2%的微小面积和功率损失。此外，冗余逻辑加法器为恒定时间内的间隔符传播铺平了道路，并为有效数据的添加积累了实际情况延迟。
A novel concept of logic redundancy insertion is presented that facilitates significant latency reduction in self-timed adder circuits. The proposed concept is universal in the sense that it can be extended to a variety of self-timed design methods. Redundant logic can be incorporated to generate efficient self-timed realizations of iterative logic specifications. Based on the case study of a 32-bit self-timed carry-ripple adder, it has been found that redundant implementations minimize the data path latency by 21.1% at the expense of increases in area and power by 2.3% and 0.8% on average compared to their nonredundant counterparts. However, when considering further peephole logic optimizations, it has been observed in a specific scenario that the delay reduction could be as high as 31% while accompanied by only meager area and power penalties of 0.6% and 1.2%, respectively. Moreover, redundant logic adders pave the way for spacer propagation in constant time and garner actual case latency for addition of valid data.