0.65–0.73THz quintupler with an on-chip antenna in 65-nm CMOS
0.65–0.73THz quintupler with an on-chip antenna in 65-nm CMOS
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0.65–0.73THz 五倍频器，带 65 nm CMOS 片上天线
DOI：
10.1109/vlsic.2015.7231303
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发表时间：
2015
期刊：
影响因子：
--
通讯作者：
K. O. Kenneth
中科院分区：
文献类型：
--
作者：
Z. Ahmad;K. O. Kenneth
本文首次在CMOS电路中实现了一种采用对称积累MOS变容管的无源五倍倍频器。采用65 nm体CMOS工艺制作的宽带（0.65-0.73THz）五倍频器，在726 GHz处的峰值有效各向同性辐射功率（EIRP）为-22dBm，最小转换损耗为34 dB。这种在CMOS中实现的最高阶乘法器在任何基于硅的无透镜信号产生电路中具有最高的EIRP，该电路工作在500 GHz以上。
A passive frequency quintupler using a symmetric accumulation MOS varactor is demonstrated for the first time in CMOS. The broadband (0.65-0.73THz) quintupler with an on-chip antenna fabricated in a 65-nm bulk CMOS process reaches a setup limited peak Effective Isotropic Radiated Power (EIRP) of -22dBm at 726GHz, and a minimum conversion loss of 34dB. This highest order multiplier realized in CMOS has the highest EIRP among any lens-less silicon based signal generation circuit operating above 500GHz.