4H-SiC Power MOSFET Blocking 1200V with a Gate Technology Compatible with Industrial Applications
4H-SiC Power MOSFET Blocking 1200V with a Gate Technology Compatible with Industrial Applications
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采用与工业应用兼容的栅极技术的 4H-SiC 功率 MOSFET 阻断 1200V
DOI：
10.4028/www.scientific.net/msf.433-436.769
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
D. Stephani
中科院分区：
文献类型：
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作者：
D. Peters;A. Schöner;P. Friedrichs;D. Stephani
介绍了一种阻断1200 V的常关断型4 H-SiC功率MOSFET。它的结构、工艺和电极材料设计尽可能接近标准硅功率MOSFET，特别是栅电极采用多晶硅材料。栅极氧化物通过在一氧化二氮中氧化来制备。为了使器件与功率电子的标准栅极驱动器兼容，栅极氧化层厚度增加到72 nm。关于长期稳定性，器械的特征在于最大氧化物场强为2.5 MV/cm。详细分析了开关特性。引言最近报道了通过使用栅极氧化物氮化来改善4 H-SiC金属氧化物半导体场效应晶体管（MOSFET）的反型层迁移率[1-4]。在低掺杂p型外延层上制备的横向4 H-MOSFET的值高达48 cm/Vs。这是值得注意的，因为氧气的热氧化值通常低于1cm/Vs。对于垂直MOSFET，尽管4 H-SiC具有高体迁移率，但从反型沟道迁移率的角度来看，4 H-SiC被视为最差的选择。如[5]中艾德指出的，反型沟道迁移率强烈地依赖于多型体。这种效应很可能是由能量固定在价带上方约2.9 eV的碳相关表面态引起的。取决于多型体的带隙，它们充当近界面阱，或多或少与导带边缘重叠。因此，使用15 R和6 H-SiC多型体可以实现更高的沟道迁移率。但另一方面，平行于c轴的6 H-SiC的体迁移率要低得多，使得6 H-SiC更适合于功率器件。15 R-SiC将是最佳选择，但尚未商业化。本文将通过氮化形成栅极氧化物的方法[ 1]与[6]中描述的垂直SiC功率MOSFET开发的技术相结合。在这种情况下，使用多晶硅栅极，这是硅功率MOSFET技术的标准。此外，栅极氧化层厚度显著增加，以满足工业功率应用的要求：与标准栅极驱动电路（栅源电压在±20 V内）的兼容性，以及通过严格限制氧化层场强至2.5 MV/cm获得的长期稳定性。图1中描绘了所谓的三重注入垂直MO SFET的单元结构。可以容易地想象，结构、工艺和电极材料被设计为尽可能接近众所周知的硅DMOS。该器件是平面的，因此可用于制造。表1列出了特征设计数据。特别地，如果反型层主导导通电阻，则重要的是实现尽可能均匀的栅极长度。为此，已经开发了自对准工艺。MOSFET单元的p型体二极管以及n型源极注入仅由一个掩模限定。Materials Science Forum Online：2003-09-15 ISSN：1662-9752，Vols. 433-436，pp 769-772 doi：10.4028/www.scientific.net/MSF.433-436.769 © 2003 Trans Tech Publications Ltd，Switzerland版权所有。未经Trans Tech Publications Ltd（www.scientific.net）的书面许可，不得以任何形式或任何方式复制或传播本文的任何内容。（Semanticscholar.org-12/03/20，10：57：02）沟道区中的铝掺杂分布从表面处的1 × 1017 cm增加到0.4 μm深度处的1 × 1017 cm。栅极氧化物在1250°C下在一氧化二氮气氛中热生长。栅电极由掺磷多晶硅组成，它可以很容易地通过热氧化与源极金属化绝缘。除了栅电极的图案化之外，所有其他掩模级都需要较小的掩模对准精度。设计数据有源区1.39 mm芯片面积2.25 mm沟道宽度18 cm沟道长度1.5 μm电池尺寸24 x 24 μm电池数量2419氧化层厚度72 nm n漂移区厚度10.5 μm n漂移区掺杂6 x 10 cm功率MOSFET的设计数据图1：MOSFET单元横截面（正方形布局，单元网格24 μm）a）B）图2：垂直功率MOSFET在结温a）25°C和B）125°C时的通态输出特性施加0、6、12、18、24 V的栅源电压。通态I-V特性的结果和讨论。图2示出了在晶片级上测量的导通状态特性。对于两种结温（25°C和125°C），器件均为常关，这是电源应用的重要特性。栅极源极电压V GS以6 V的步长被驱动至24 V。对应于2.5 MV/cm的氧化物场强，VGS = 18 V的g_（max）应被视为正常操作的上限。在这种情况下，栅极-源极绝缘多晶硅栅极漏极接触源极接触SiC衬底n外延层n+源极p基极p阱栅极氧化物的氧化物厚度0 1 2 3 4 5 0. 0 0. 5 1. 0 1. 5 GS
A normally off 4H-SiC power MOSFET blocking 1200 V is presented. Its structure, process and electrode materials are designed as close as possible to that of standard Si power MOSFETs, especially the gate electrode is made of pol ycrystalline silicon. The gate oxide is prepared by oxidation in nitrous oxide. In order to make the device compatible with standard gate drivers for power electronics the gate oxide thicknes s has been increased to 72 nm. With respect to long term stability the device is character ized at a maximum oxide field strength of 2.5 MV/cm. Onand off-state characteristics are presented and analy zed in detail. Introduction Improvements of the inversion layer mobility of 4H-SiC metal oxide semiconductor field effect transistors (MOSFETs) were reported recently by using gate oxide nitridation [1-4]. Values up to 48 cm/Vs resulted for lateral 4H-MOSFETs prepared on low doped p-type epilayers. This is remarkable since with thermal oxidation by oxy gen values below 1 cm /Vs were typical. For vertical MOSFETs 4H-SiC was seen as the worst choice from inversion channel mobility point of view, in spite of its high bulk mobility. As point ed out in [5], the inversion channel mobility strongly depends on the polytype. This effect i s most likely caused by carbon related surface states energetically fixed to around 2.9 eV above the valence band. Depending on the band gap of the polytype they act as near interface t raps, more or less overlapping with the conduction band edge. Consequently a higher channel mobility can be achieved using 15Rand 6H-SiC polytypes. But on the other hand the bulk mobilit y f 6HSiC parallel to the c-axis is much lower and makes 6H-SiC les s suitable for power devices. 15R-SiC would be the best choice but is not commercially available. This paper combines the method of forming a gate oxide by nitridation [ 1] with the technology developed for vertical SiC power MOSFETs described in [6]. In this case a polycrystalline silicon gate was used which is standard for sili con power MOSFET technology. Furthermore, the gate oxide thickness was significantly increased in order to meet the requirements of industrial power applications: compatibility wit h standard gate driving circuitry (gate source voltages within ±20 V) and long term stability obtained by strictly limiting the oxide field strength to 2.5 MV/cm. Device and Fabrication A cell structure of the so called triple implanted vertical MO SFET is sketched in Fig. 1. One can easily imagine that structure, process and electr od materials are designed as close as possible to the well known silicon DMOS. The device is planar and thus favora ble f fabrication. Characteristic design data are listed in Table 1. I n particular, if the inversion layer dominates the on-resistance it is important to achieve a gate le ngth as homogeneous as possible. For this purpose a self aligning process has been developed. The p-type body diode as well as the n-type source implantation of the MOSFET cell a re defined by only one mask. Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 769-772 doi:10.4028/www.scientific.net/MSF.433-436.769 © 2003 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific.net. (Semanticscholar.org-12/03/20,10:57:02) The aluminum doping profile in the channel region increases from 1x10 17 cm at the surface to 1x10 cm in a depth of 0.4 μm. The gate oxide is thermally grown in nitrous oxi de atmosphere at 1250°C. The gate electrode consists of phosphorous doped polycryst alline silicon which can easily be insulated to the source metalization by thermal oxidation. Except the patterning of the gate electrodes all other mask levels requi re minor precision for mask alignment. The total process needs 11 mask levels including a final photoimide passivati on. Design Data Active area 1.39 mm Chip area 2.25 mm Channel width 18 cm Channel length 1.5 μm Cell size 24 x 24 μm Number of cells 2419 Oxide thickness 72 nm n drift zone thickness 10.5 μm n drift zone doping 6 x 10 cm Table 1: Design data of the power MOSFET Fig. 1: MOSFET cell cross section (square layout, cell grid 24 μm) a) b) Fig. 2: On-state output characteristics of the vertical power MOSFET at a junction temperature of a) 25°C and b) 125°C. Gate source voltages of 0, 6, 12, 18, 24 V were applied. Results and Discussion On-state I-V-characteristics. Fig. 2 shows the on-state characteristics measured on wafer level. For both junction temperatures (25°C and 125°C) the device is normally off, an important feature for power applications. The gate source voltage V GS is driven up to 24 V in steps of 6 V. Corresponding to an oxide field strength of 2.5 MV/cm the g raph for VGS = 18 V should be taken as an upper limit for normal operation. In this case the oxide thickness of Gate-Source-Insulation Poly-Si Gate Drain Contact Source Contact SiC Substrate nEpilayer n+Source p-Base p-Well Gate Oxide 0 1 2 3 4 5 0.0 0.5 1.0 1.5 GS