Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs
Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs
复制标题
您的巴士仲裁员真的公平吗？
DOI：
10.1145/3358183
复制
发表时间：
2019
期刊：
影响因子：
--
通讯作者：
G. Buttazzo
中科院分区：
文献类型：
--
作者：
Francesco Restuccia;Marco Pagani;Alessandro Biondi;Mauro Marinoni;G. Buttazzo
AMBA AXI是一种流行的总线协议，在现场可编程门阵列片上系统(FPGA SoC)中被广泛采用作为交换数据的媒介。AXI协议没有规定如何仲裁冲突的事务，因此，总线仲裁器的设计留给了采用AXI的供应商。通常，对于Xilinx流行的SoC，实现循环仲裁以确保主节点公平地访问总线。本文解决了在循环仲裁下采用AXI协议时可能出现的一个关键问题；具体地说，是在存在具有不同突发大小的总线事务的情况下。首先，证明了在某些配置下可以实现完全不公平的带宽分配，使得任意减少目标主节点的总线带宽成为可能。这个问题引起了严重的性能、安全和安全问题。其次，提出了一种低延迟(一个时钟周期)的AXI突发均衡器(ABE)模块来恢复公平性。我们的研究和建议得到了三个现代SoC的实现和测试的支持。报告的实验结果证实了该问题的存在，并评估了使用Xilinx IP库中的总线流量生成器和硬件加速器的ABE的有效性。
AMBA AXI is a popular bus protocol that is widely adopted as the medium to exchange data in field-programmable gate array system-on-chips (FPGA SoCs). The AXI protocol does not specify how conflicting transactions are arbitrated and hence the design of bus arbiters is left to the vendors that adopt AXI. Typically, a round-robin arbitration is implemented to ensure a fair access to the bus by the master nodes, as for the popular SoCs by Xilinx. This paper addresses a critical issue that can arise when adopting the AXI protocol under round-robin arbitration; specifically, in the presence of bus transactions with heterogeneous burst sizes. First, it is shown that a completely unfair bandwidth distribution can be achieved under some configurations, making possible to arbitrarily decrease the bus bandwidth of a target master node. This issue poses serious performance, safety, and security concerns. Second, a low-latency (one clock cycle) module named AXI burst equalizer (ABE) is proposed to restore fairness. Our investigations and proposals are supported by implementations and tests upon three modern SoCs. Experimental results are reported to confirm the existence of the issue and assess the effectiveness of the ABE with bus traffic generators and hardware accelerators from the Xilinx’s IP library.
异构 MPSoC 架构上并发应用的运行时可重配置总线仲裁
DOI：
10.1109/dsd.2014.105
发表时间：
2014
期刊：
2014 17th Euromicro Conference on Digital System Design
影响因子：
--
作者：
É. Sousa;D. Gangadharan;F. Hannig;J. Teich
通讯作者：
J. Teich